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PRELIMINARY
AM29PDL128G
128 Megabit (8 M x 16-Bit/4 M x 32-Bit) CMOS 3.0 Volt-only, Simultaneous Read/ Write Flash Memory with VersatileIOTM Control
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
s 128Mbit Page Mode device
-- Word (16-bit) or double word (32-bit) mode selectable via WORD# input -- Page size of 8 words/4 double words: Fast page read access from random locations within the page
SOFTWARE FEATURES
s Software command-set compatible with JEDEC 42.4 standard
-- Backward compatible with Am29F and Am29LV families
s CFI (Common Flash Interface) complaint
-- Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices
s Single power supply operation
-- Full Voltage range: 2.7 to 3.6 volt read, erase, and program operations for battery-powered applications
s Erase Suspend / Erase Resume
-- Suspends an erase operation to allow read or program operations in other sectors of same bank
s Simultaneous Read/Write Operation
-- Data can be continuously read from one bank while executing erase/program functions in another bank -- Zero latency switching from write to read operations
s Unlock Bypass Program command
-- Reduces overall programming time when issuing multiple program command sequences
s FlexBank Architecture
-- 4 separate banks, with up to two simultaneous operations per device -- Organized as two 16 Mbit banks (Bank 1 & 4) and two 48 Mbit banks (Bank 2 & 3)
HARDWARE FEATURES
s Ready/Busy# pin (RY/BY#)
-- Provides a hardware method of detecting program or erase cycle completion
s VersatileI/O
TM
(VIO) Control
-- Output voltage generated and input voltages tolerated on the device is determined by the voltage on the VIO pin
s Hardware reset pin (RESET#)
-- Hardware method to reset the device to reading array data
s SecSi (Secured Silicon) Sector region
-- 128 words (64 double words) accessible through a command sequence
s WP# (Write Protect) input
-- At VIL, protects the two top and two bottom sectors, regardless of sector protect/unprotect status -- At VIH, allows removal of sector protection -- An internal pull up to Vcc is provided
s Both top and bottom boot blocks in one device s Manufactured on 0.17 m process technology s 20-year data retention at 125C s Minimum 1 million write cycle guarantee per sector
s Persistent Sector Protection
-- A command sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector -- Sectors can be locked and unlocked in-system at VCC level
PERFORMANCE CHARACTERISTICS
s High Performance
-- Page access times as fast as 25 ns -- Random access times as fast as 70 ns
s Password Sector Protection
-- A sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password
s Power consumption (typical values at 10 MHz)
-- 38 mA active read current -- 17 mA program/erase current -- 1.5 A typical standby mode current
s ACC (Acceleration) input provides faster programming times in a factory setting s Package options
-- 80-ball Fortified BGA
This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
Publication# 25685 Rev: B Amendment/+2 Issue Date: July 29, 2002
Refer to AMD's Website (www.amd.com) for the latest information.
PRELIMINARY
GENERAL DESCRIPTION
The AM29PDL128G is a 128 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory device organized as 8 Mwords or 4 M double words (One word is equal to two bytes). The device is offered in an 80-ball Fortified BGA package. The word-wide data (x16) appears on DQ15-DQ0; the double word mode data (x32) appears on DQ31-DQ0. This device can be programmed in-system or in standard EPROM programmers. A 12.0 V V PP is not required for write or erase operations. The device offers fast page access times of 25 and 30 ns, with corresponding random access times of 70 and 80 ns, respectively, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.
Standard Flash Memory Features
The device requires a single 3.0 volt power supply (2.7 V to 3.6 V) for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC 42.4 single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the SecSi Sector area (One Time Program area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. AMD's Flash technology combined years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.
Simultaneous Read/Write Operation with Zero Latency
The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into 4 banks, which can be considered to be four separate memory arrays as far as certain operations are concerned. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank with zero latency (with 2 simultaneous operations operating at any one time). This releases the system from waiting for the completion of a program or erase operation, greatly improving system performance. The device can be organized in both top and bottom sector configurations (see Table 1). Bank/Sector Sizes Number of Sectors 8 31 96 96 8 31 Sector Size (Word/Dbl. Word) 4/2 32/16 32/16 32/16 4/2 32/16
Bank 1 2 3 4
Bank Size 16 Mbit 48 Mbit 48 Mbit 16 Mbit
Page Mode Features
The device is AC timing, input/output, and package compatible with 8 Mbit x16 page mode mask ROM. The page size is 8 words or 4 double words. After initial page access is accomplished, the page mode operation provides fast read access speed of random locations within that page.
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PRELIMINARY
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Simultaneous Operation Block Diagram . . . . . . . 6 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 7 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9 Device Bus Operations . . . . . . . . . . . . . . . . . . . . 10
Table 1. AM29PDL128G Device Bus Operations ...........................10 Table 11. System Interface String................................................... 31
Word/Double Word Configuration........................................... 10 Requirements for Reading Array Data ................................... 10 Random Read (Non-Page Read) ........................................... 10 Page Mode Read .................................................................... 11
Table 2. Page Select, Double Word Mode ......................................11 Table 3. Page Select, Word Mode ..................................................11
Table 12. Device Geometry Definition................................. 32 Table 13. Primary Vendor-Specific Extended Query........... 33 Command Definitions. . . . . . . . . . . . . . . . . . . . . . 34 Reading Array Data ................................................................ 34 Reset Command ..................................................................... 34 Autoselect Command Sequence ............................................ 34 Enter SecSi Sector/Exit SecSi Sector Command Sequence .............................................................. 34 Double Word/Word Program Command Sequence ................ 35 Unlock Bypass Command Sequence ..................................... 35
Figure 3. Program Operation ......................................................... 36
Chip Erase Command Sequence ........................................... 36 Sector Erase Command Sequence ........................................ 36 Erase Suspend/Erase Resume Commands ........................... 37
Figure 4. Erase Operation.............................................................. 37
Simultaneous Operation ......................................................... 11
Table 4. Bank Select .......................................................................11
Writing Commands/Command Sequences ............................ 11 Accelerated Program Operation ............................................. 12 Autoselect Functions .............................................................. 12 Standby Mode ........................................................................ 12 Automatic Sleep Mode ........................................................... 12 RESET#: Hardware Reset Pin ............................................... 12 Output Disable Mode .............................................................. 12
Table 5. Sector Address Table ........................................................13 Table 6. SecSi Sector Addresses ................................................20
Autoselect Mode..................................................................... 20
Table 7. Autoselect Codes (High Voltage Method) ........................20 Table 8. Sector Block Addresses for Protection/Unprotection ........21
Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . 23 Persistent Sector Protection ................................................... 24 Persistent Protection Bit (PPB) ............................................... 24 Persistent Protection Bit Lock (PPB Lock) ............................. 24 Dynamic Protection Bit (DYB) ................................................ 24
Table 9. Sector Protection Schemes ...............................................25
Password Program Command ................................................ 37 Password Verify Command .................................................... 38 Password Protection Mode Locking Bit Program Command .. 38 Persistent Sector Protection Mode Locking Bit Program Command ............................................................................... 38 SecSi Sector Protection Bit Program Command .................... 38 PPB Lock Bit Set Command ................................................... 38 DYB Write Command ............................................................. 39 Password Unlock Command .................................................. 39 PPB Program Command ........................................................ 39 All PPB Erase Command ........................................................ 39 DYB Write Command ............................................................. 39 PPB Lock Bit Set Command ................................................... 40 PPB Lock Bit Status Command .............................................. 40 Sector Protection Status Command ....................................... 40 Command Definitions Tables.................................................. 41
Table 14. Memory Array Command Definitions (x32 Mode) .......... 41 Table 15. Sector Protection Command Definitions (x32 Mode) ..... 42 Table 16. Memory Array Command Definitions (x16 Mode) .......... 43 Table 17. Sector Protection Command Definitions (x16 Mode) ..... 44
Persistent Sector Protection Mode Locking Bit ...................... 25 Password Protection Mode ..................................................... 25 Password and Password Mode Locking Bit ........................... 25 64-bit Password ...................................................................... 26 Write Protect (WP#) ................................................................ 26 Persistent Protection Bit Lock ................................................. 26 High Voltage Sector Protection .............................................. 26
Figure 1. In-System Sector Protection/ Sector Unprotection Algorithms ...................................................... 27
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 45 DQ7: Data# Polling ................................................................. 45
Figure 5. Data# Polling Algorithm .................................................. 45
RY/BY#: Ready/Busy#............................................................ 46 DQ6: Toggle Bit I .................................................................... 46
Figure 6. Toggle Bit Algorithm........................................................ 46
Temporary Sector Unprotect .................................................. 28
Figure 2. Temporary Sector Unprotect Operation........................... 28
SecSiTM (Secured Silicon) Sector Flash Memory Region ............................................................ 28 SecSi Sector Protection Bit .................................................... 29 Utilizing Password and SecSi Sector Concurrently ................ 29 Hardware Data Protection ...................................................... 29 Low VCC Write Inhibit ............................................................ 29 Write Pulse "Glitch" Protection ............................................... 29 Logical Inhibit .......................................................................... 29 Power-Up Write Inhibit ............................................................ 29 Common Flash Memory Interface (CFI) . . . . . . . 30 Table 10. CFI Query Identification String ............................ 30
DQ2: Toggle Bit II ................................................................... 47 Reading Toggle Bits DQ6/DQ2 ............................................... 47 DQ5: Exceeded Timing Limits ................................................ 47 DQ3: Sector Erase Timer ....................................................... 47
Table 18. Write Operation Status ................................................... 48
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 49
Figure 7. Maximum Negative Overshoot Waveform ...................... 49 Figure 8. Maximum Positive Overshoot Waveform........................ 49
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 50 Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 9. Test Setup...................................................................... 51 Figure 10. Input Waveforms and Measurement Levels ................. 51
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 52 Read-Only Operations ........................................................... 52
Figure 11. Read Operation Timings ............................................... 52 Figure 12. Page Read Operation Timings...................................... 53
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PRELIMINARY Hardware Reset (RESET#) .................................................... 54
Figure 13. Reset Timings ................................................................ 54 Figure 24. Sector/Sector Block Protect and Unprotect Timing Diagram ............................................................. 62
Word/Double Word Configuration (WORD#) .......................... 55
Figure 14. WORD# Timings for Read Operations........................... 55 Figure 15. WORD# Timings for Write Operations........................... 55
Alternate CE# Controlled Erase and Program Operations ..... 63
Figure 25. Alternate CE# Controlled Write (Erase/Program) Operation Timings.......................................................................... 64
Erase and Program Operations .............................................. 56
Figure 16. Program Operation Timings........................................... 57 Figure 17. Accelerated Program Timing Diagram........................... 57 Figure 18. Chip/Sector Erase Operation Timings ........................... 58 Figure 19. Back-to-back Read/Write Cycle Timings ....................... 59 Figure 20. Data# Polling Timings (During Embedded Algorithms).. 59 Figure 21. Toggle Bit Timings (During Embedded Algorithms)....... 60 Figure 22. DQ2 vs. DQ6.................................................................. 60
Temporary Sector Unprotect .................................................. 61
Figure 23. Temporary Sector Unprotect Timing Diagram ............... 61
Erase And Programming Performance. . . . . . . . 65 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 65 TSOP Pin and BGA Package Capacitance . . . . . 65 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 67 LAB080--80-Ball Fortified Ball Grid Array 10 x 15 mm package .............................................................. 67 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 68
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PRELIMINARY
PRODUCT SELECTOR GUIDE
Part Number Speed Option Voltage Range: VCC = 3.0-3.6 V Voltage Range: VCC = 2.7-3.6 V Max Access Time, ns (tACC) Max CE# Access, ns (tCE) Max Page Access, ns (tPACC) Max OE# Access, ns (tOE) Note: See AC Characteristics section for full specifications. 70R 70 70 70 25 25 80 80 80 30 30 90 90 90 35 40 AM29PDL128G
BLOCK DIAGRAM
DQ31-DQ0 RY/BY# (Note 2) VCC VSS Sector Switches
VIO
RESET# Erase Voltage Generator WE# State Control Command Register CE# OE# PGM Voltage Generator
Input/Output Buffers
Chip Enable Output Enable Logic
A3, A4
STB Data Latch
VCC Detector
Timer
STB Address Latch
Y-Decoder
Y-Gating
A21-A2
X-Decoder
Cell Matrix
A1-A0 (A-1)
Notes: 1. In double word mode, input/outputs are DQ31-DQ0, address range is A21-A0. In word mode, input/outputs are DQ15-DQ0, address range is A21-A-1. 2. RY/BY# is an open drain output.
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PRELIMINARY
SIMULTANEOUS OPERATION BLOCK DIAGRAM
VCC VSS
OE# DW/W#
Mux A21-A0
Bank 1 Address
Bank 1 Y-gate X-Decoder
A21-A0
RY/BY#
Bank 2 Address
Bank 2 X-Decoder DQ31-DQ0
A21-A0 RESET# WE# CE# DW/W# WP# ACC DQ0-DQ15 X-Decoder A21-A0
Bank 3 Address
STATE CONTROL & COMMAND REGISTER
Status DQ31-DQ0 Control DQ31-DQ0 Mux
Bank 3 Y-gate
X-Decoder A21-A0 Mux
Bank 4 Address
Bank 4
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DQ31-DQ0
DQ31-DQ0
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PRELIMINARY
CONNECTION DIAGRAMS
80-Ball Fortified BGA Top View, Balls Facing Down
A8 OE# A7 WORD# A6 A21 A5 RFU A4 RY/BY# A3 A2 A2 A4 A1 A5
B8 VSS B7 CE# B6 A20 B5 WP# B4 A0 B3 A3 B2 VCC B1 DQ0
C8 DQ30 C7 DQ15 C6
D8 VIO D7 VSS D6
E8 DQ28 E7 DQ13 E6 DQ12 E5 ACC E4 RESET# E3 DQ4 E2 DQ3 E1 DQ19
F8 DQ11 F7 DQ26 F6 DQ27 F5 RFU F4 RFU F3 DQ20 F2 DQ21 F1 DQ5
G8 VSS G7 VIO G6 DQ25 G5 DQ10 G4 VSS G3 DQ22 G2 DQ6 G1 VIO
H8 DQ9 H7 DQ24 H6 DQ8 H5 A14 H4 A12 H3 VSS H2 DQ23 H1 DQ7
J8 VCC J7 A19 J6 A16 J5 A13 J4 RFU J3 A10 J2 A7 J1 A6
K8 A18 K7 A17 K6 A15 K5 RFU K4 RFU K3 A11 K2 A9 K1 A8
DQ31/A-1 DQ14 C5 WE# C4 A1 C3 DQ16 C2 DQ1 C1 DQ17 D5 DQ29 D4 DQ18 D3 VSS D2 VIO D1 DQ2
Special Handling Instructions for BGA Packages
Special handling is required for Flash Memory products in molded packages (TSOP, BGA, PLCC, PDIP,
SSOP). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time.
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PRELIMINARY
PIN DESCRIPTION
A21-A0 = 22 Addresses 31 Data Inputs/Outputs DQ31 (Data Input/Output, double word mode), A-1 (LSB Address Input, word mode) Chip Enable Output Enable Write Enable DQ30-DQ0 = DQ31/A-1 =
LOGIC SYMBOL
22 A21-A0 DQ31-DQ0 (A-1) CE# OE# WE# WP# 32 or 16
CE# OE# WE# WP# ACC RESET# WORD#
= = = = = = =
Hardware Write Protect Input Acceleration Input Hardware Reset Pin, Active Low Word Enable Input At VIL, selects 16-bit mode, At VIH, selects 32-bit mode Ready/Busy Output 3.0 Volt-only Single Power Supply (see Product Selector Guide for speed options and voltage supply tolerances) Output Buffer Power Supply Device Ground Pin Not Connected Internally Reserved for Future Use
ACC RESET# WORD# VIO RY/BY#
RY/BY# VCC
= =
VIO VSS NC RFU
= = = =
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PRELIMINARY
ORDERING INFORMATION Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: AM29PDL128G 70 PE I
OPTIONAL PROCESSING Blank = Standard Processing N = 16-byte ESN devices (Contact an AMD representative for more information) TEMPERATURE RANGE I = Industrial (-40C to +85C) E = Extended (-55C to +125C) PACKAGE TYPE PE = 80-Ball Fortified Ball Grid Array (FBGA) 1 mm pitch, 15 x 10 mm package (LAB080) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER/DESCRIPTION AM29PDL128G 128 Megabit (8 M x 16-Bit/4 M x 32-Bit) CMOS Flash Memory 3.0 Volt-only Read, Program, and Erase Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
Valid Combinations for BGA Packages Order Number AM29PDL128G70R AM29PDL128G70 AM29PDL128G80 AM29PDL128G90 PEI PEI, PEE Package Marking PD128G70R PD128G70V PD128G80V PD128G90V I I, E
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PRELIMINARY
DEVICE BUS OPERATIONS
This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The contents of the Table 1. register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.
AM29PDL128G Device Bus Operations
DQ31-DQ16
Operation Read Write Standby Output Disable Reset Temporary Sector Unprotect (High Voltage)
CE# L L VCC 0.3 V L X X
OE# L H X H X X
WE# H L X H X X
RESET# H H VCC 0.3 V H L VID
WP# X X X X X X
Addresses (Note 1) AIN AIN X X X AIN
WORD# = VIH DOUT DIN High-Z High-Z High-Z DIN
WORD# = VIL DQ30-DQ16 = High-Z, DQ31 = A-1 High-Z High-Z High-Z X
DQ15- DQ0 DOUT DIN High-Z High-Z High-Z DIN
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5-12.5 V, VHH = 9.0 0.5 V, X = Don't Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Addresses are A21-A0 in double word mode (WORD# = VIH), A21-A-1 in word mode (WORD# = VIL). 2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the "Sector Protection" section.
Word/Double Word Configuration
The WORD# pin controls whether the device data I/O pins operate in the word or double word configuration. If the WORD# pin is set at VIH, the device is in double word configuration, DQ31-DQ0 are active and controlled by CE# and OE#. If the WORD# pin is set at VIL, the device is in word configuration, and only data I/O pins DQ15-DQ0 are active and controlled by CE# and OE#. The data I/O pins DQ30-DQ16 are tri-stated, and the DQ31 pin is used as an input for the least significant address bit (LSB) function, which is named A-1.
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. Refer to the AC Read-Only Operations table for timing specifications and to Figure 11 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data. Random Read (Non-Page Read) Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (t CE ) is the delay from the stable addresses and stable CE# to valid data at the output inputs. The output enable access time is the delay from the falling edge of the OE# to valid data at the output
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at V IH . The WORD# pin determines whether the device outputs array data in words or double words.
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PRELIMINARY inputs (assuming the addresses have been stable for at least tACC-tOE time). Page Mode Read The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. The page size of the device is 8 words, or 4 double words, with the appropriate page being selected by the higher address bits A21-A2 and the LSB bits A1-A0 (in the double word mode) and A1 to A-1 (in the word mode) determining the specific word/double word within that page. This is an asynchronous operation with the microprocessor supplying the specific word or double word location. The random or initial page access is equal to tACC or tCE and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to tPACC. When CE# is deasserted and reasserted for a subsequent access, the access time is tACC or tCE. Here again, CE# selects the device and OE# is the output control and should be used to gate data to the output inputs if the device is selected. Fast page mode accesses are obtained by keeping A21-A2 constant and changing A1 to A0 to select the specific double word, or changing A1 to A-1 to select the specific word, within that page. Table 2.
Word Double Word 0 Double Word 1 Double Word 2 Double Word 3
Simultaneous Operation
The device is capable of reading data from one bank of memory while a program or erase operation is in progress in another bank of memory (simultaneous operation), in addition to the conventional features (read, program, erase-suspend read, and erase-suspend program). The bank selected can be selected by bank addresses (A21-A19) with zero latency. The simultaneous operation can execute multi-function mode in the same bank. Table 4.
Bank Bank 1 Bank 2 Bank 3 Bank 4
Bank Select
A21-A19 000 001, 010, 011 100, 101, 110 111
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. For program operations, the WORD# pin determines whether the device accepts program data in double words or words. Refer to "Word/Double Word Configuration" for more information. The device features an Unlock Bypass mode to facilitate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are required to program a double word or word, instead of four. The "Double Word/Word Program Command Sequence" section has details on programming data to the device using both standard and Unlock Bypass command sequences.
Page Select, Double Word Mode
A1 0 0 1 1 A0 0 1 0 1
Table 3.
Word Word 0 Word 1 Word 2 Word 3 Word 4 Word 5 Word 6 Word 7
Page Select, Word Mode
A1 0 0 0 0 1 1 1 1 A0 0 0 1 1 0 0 1 1 A-1 0 1 0 1 0 1 0 1
An erase operation can erase one sector, multiple sectors, or the entire device. Table 5 indicates the address space that each sector occupies. A "bank address" is the address bits required to uniquely select a bank. Similarly, a "sector address" refers to the address bits required to uniquely select a sector. The "Command Definitions" section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations.
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PRELIMINARY Accelerated Program Operation The device offers accelerated program operations through the ACC function. This function is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the ACC pin returns the device to normal operation. Note that VHH must not be asserted on ACC for operations other than accelerated programming, or device damage may result. Autoselect Functions If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ15-DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information. this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. Note that during automatic sleep mode, OE# must be at VIH before the device reduces current to the stated sleep mode specification. ICC5 in the DC Characteristics table represents the automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a "0" (busy) until the internal reset operation is complete, which requires a time of t READY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is "1"), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# parameters and to Figure 13 for the timing diagram.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (t CE ) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in the DC Characteristics table represents the CMOS standby current specification.
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins (except for RY/BY#) are placed in the high impedance state.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables
12
AM29PDL128G
July 29, 2002
PRELIMINARY Table 5.
Sector Address (A21-A11) 00000000000 00000000001 00000000010 00000000011 00000000100 00000000101 00000000110 00000000111 00000001XXX 00000010XXX 00000011XXX 00000100XXX 00000101XXX 00000110XXX 00000111XXX 00001000XXX 00001001XXX 00001010XXX 00001011XXX 00001100XXX 00001101XXX 00001110XXX 00001111XXX 00010000XXX 00010001XXX 00010010XXX 00010011XXX 00010100XXX 00010101XXX 00010110XXX 00010111XXX 00011000XXX 00011001XXX 00011010XXX 00011011XXX 00011100XXX 00011101XXX 00011110XXX 00011111XXX
Sector Address Table
Sector Size (Kwords/ Kdoublewords) 4/2 4/2 4/2 4/2 4/2 4/2 4/2 4/2 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 Address Range (x16) 00000h-00FFFh 01000h-01FFFh 02000h-02FFFh 03000h-03FFFh 04000h-04FFFh 05000h-05FFFh 06000h-06FFFh 07000h-07FFFh 08000h-0FFFFh 10000h-17FFFh 18000h-1FFFFh 20000h-27FFFh 28000h-2FFFFh 30000h-37FFFh 38000h-3FFFFh 40000h-47FFFh 48000h-4FFFFh 50000h-57FFFh 58000h-5FFFFh 60000h-67FFFh 68000h-6FFFFh 70000h-77FFFh 78000h-7FFFFh 80000h-87FFFh 88000h-8FFFFh 90000h-97FFFh 98000h-9FFFFh A0000h-A7FFFh A8000h-AFFFFh B0000h-B7FFFh B8000h-BFFFFh C0000h-C7FFFh C8000h-CFFFFh D0000h-D7FFFh D8000h-DFFFFh E0000h-E7FFFh E8000h-EFFFFh F0000h-F7FFFh F8000h-FFFFFh Address Range (x32) 000000h-0007FFh 000800h-000FFFh 001000h-0017FFh 001800h-001FFFh 002000h-0027FFh 002800h-002FFFh 003000h-0037FFh 003800h-003FFFh 004000h-007FFFh 008000h-00BFFFh 00C000h-00FFFFh 010000h-013FFFh 014000h-017FFFh 018000h-01BFFFh 01C000h-01FFFFh 020000h-023FFFh 024000h-027FFFh 028000h-02BFFFh 02C000h-02FFFFh 030000h-033FFFh 034000h-037FFFh 038000h-03BFFFh 03C000h-03FFFFh 040000h-043FFFh 044000h-047FFFh 048000h-04BFFFh 04C000h-04FFFFh 050000h-053FFFh 054000h-057FFFh 058000h-05BFFFh 05C000h-05FFFFh 060000h-063FFFh 064000h-067FFFh 068000h-06BFFFh 06C000h-06FFFFh 070000h-073FFFh 074000h-077FFFh 078000h-07BFFFh 07C000-07FFFFh
Bank
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17
Bank 1
SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38
July 29, 2002
AM29PDL128G
13
PRELIMINARY Table 5.
Sector Address (A21-A11) 00100000XXX 00100001XXX 00100010XXX 00100011XXX 00100100XXX 00100101XXX 00100110XXX 00100111XXX 00101000XXX 00101001XXX 00101010XXX 00101011XXX 00101100XXX 00101101XXX 00101110XXX 00101111XXX 00110000XXX 00110001XXX 00110010XXX 00110011XXX 00110100XXX 00110101XXX 00110110XXX 00110111XXX 00111000XXX 00111001XXX 00111010XXX 00111011XXX 00111100XXX 00111101XXX 00111110XXX 00111111XXX 01000000XXX 01000001XXX 01000010XXX 01000011XXX 01000100XXX 01000101XXX 01000110XXX 01000111XXX 01001000XXX 01001001XXX
Sector Address Table (Continued)
Sector Size (Kwords/ Kdoublewords) 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 Address Range (x16) 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh 200000h-207FFFh 208000h-20FFFFh 210000h-217FFFh 218000h-21FFFFh 220000h-227FFFh 228000h-22FFFFh 230000h-237FFFh 238000h-23FFFFh 240000h-247FFFh 248000h-24FFFFh Address Range (x32) 080000h-083FFFh 084000h-087FFFh 088000h-08BFFFh 08C000h-08FFFFh 090000h-093FFFh 094000h-097FFFh 098000h-09BFFFh 09C000h-09FFFFh 0A0000h-0A3FFFh 0A4000h-0A7FFFh 0A8000h-0ABFFFh 0AC000h-0AFFFFh 0B0000h-0B3FFFh 0B4000h-0B7FFFh 0B8000h-0BBFFFh 0BC000h-0BFFFFh 0C0000h-0C3FFFh 0C4000h-0C7FFFh 0C8000h-0CBFFFh 0CC000h-0CFFFFh 0D0000h-0D3FFFh 0D4000h-0D7FFFh 0D8000h-0DBFFFh 0DC000h-0DFFFFh 0E0000h-0E3FFFh 0E4000h-0E7FFFh 0E8000h-0EBFFFh 0EC000h-0EFFFFh 0F0000h-0F3FFFh 0F4000h-0F7FFFh 0F8000h-0FBFFFh 0FC000h-0FFFFFh 100000h-103FFFh 104000h-107FFFh 108000h-10BFFFh 10C000h-10FFFFh 110000h-113FFFh 114000h-117FFFh 118000h-11BFFFh 11C000h-11FFFFh 120000h-123FFFh 124000h-127FFFh
Bank
Sector SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58
Bank 2
SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80
14
AM29PDL128G
July 29, 2002
PRELIMINARY Table 5.
Sector Address (A21-A11) 01001010XXX 01001011XXX 01001100XXX 01001101XXX 01001110XXX 01001111XXX 01010000XXX 01010001XXX 01010010XXX 01010011XXX 01010100XXX 01010101XXX 01010110XXX 01010111XXX 01011000XXX 01011001XXX 01011010XXX 01011011XXX 01011100XXX 01011101XXX 01011110XXX 01011111XXX 01100000XXX 01100001XXX 01100010XXX 01100011XXX 01100100XXX 01100101XXX 01100110XXX 01100111XXX 01101000XXX 01101001XXX 01101010XXX 01101011XXX 01101100XXX 01101101XXX 01101110XXX 01101111XXX 01110000XXX
Sector Address Table (Continued)
Sector Size (Kwords/ Kdoublewords) 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 Address Range (x16) 250000h-257FFFh 258000h-25FFFFh 260000h-267FFFh 268000h-26FFFFh 270000h-277FFFh 278000h-27FFFFh 280000h-287FFFh 288000h-28FFFFh 290000h-297FFFh 298000h-29FFFFh 2A0000h-2A7FFFh 2A8000h-2AFFFFh 2B0000h-2B7FFFh 2B8000h-2BFFFFh 2C0000h-2C7FFFh 2C8000h-2CFFFFh 2D0000h-2D7FFFh 2D8000h-2DFFFFh 2E0000h-2E7FFFh 2E8000h-2EFFFFh 2F0000h-2F7FFFh 2F8000h-2FFFFFh 300000h-307FFFh 308000h-30FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh 330000h-337FFFh 338000h-33FFFFh 340000h-347FFFh 348000h-34FFFFh 350000h-357FFFh 358000h-35FFFFh 360000h-367FFFh 368000h-36FFFFh 370000h-377FFFh 378000h-37FFFFh 380000h-387FFFh Address Range (x32) 128000h-12BFFFh 12C000h-12FFFFh 130000h-133FFFh 134000h-137FFFh 138000h-13BFFFh 13C000h-13FFFFh 140000h-143FFFh 144000h-147FFFh 148000h-14BFFFh 14C000h-14FFFFh 150000h-153FFFh 154000h-157FFFh 158000h-15BFFFh 15C000h-15FFFFh 160000h-163FFFh 164000h-167FFFh 168000h-16BFFFh 16C000h-16FFFFh 170000h-173FFFh 174000h-177FFFh 178000h-17BFFFh 17C000h-17FFFFh 180000h-183FFFh 184000h-187FFFh 188000h-18BFFFh 18C000h-18FFFFh 190000h-193FFFh 194000h-197FFFh 198000h-19BFFFh 19C000h-19FFFFh 1A0000h-1A3FFFh 1A4000h-1A7FFFh 1A8000h-1ABFFFh 1AC000h-1AFFFFh 1B0000h-1B3FFFh 1B4000h-1B7FFFh 1B8000h-1BBFFFh 1BC000h-1BFFFFh 1C0000h-1C3FFFh
Bank
Sector SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97
Bank 2 (continued)
SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119
July 29, 2002
AM29PDL128G
15
PRELIMINARY Table 5.
Sector Address (A21-A11) 01110001XXX 01110010XXX 01110011XXX 01110100XXX 01110101XXX 01110110XXX 01110111XXX 01111000XXX 01111001XXX 01111010XXX 01111011XXX 01111100XXX 01111101XXX 01111110XXX 01111111XXX 10000000XXX 10000001XXX 10000010XXX 10000011XXX 10000100XXX 10000101XXX 10000110XXX 10000111XXX 10001000XXX 10001001XXX 10001010XXX 10001011XXX 10001100XXX 10001101XXX 10001110XXX 10001111XXX 10010000XXX 10010001XXX 10010010XXX 10010011XXX 10010100XXX 10010101XXX 10010110XXX 10010111XXX
Sector Address Table (Continued)
Sector Size (Kwords/ Kdoublewords) 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 Address Range (x16) 388000h-38FFFFh 390000h-397FFFh 398000h-39FFFFh 3A0000h-3A7FFFh 3A8000h-3AFFFFh 3B0000h-3B7FFFh 3B8000h-3BFFFFh 3C0000h-3C7FFFh 3C8000h-3CFFFFh 3D0000h-3D7FFFh 3D8000h-3DFFFFh 3E0000h-3E7FFFh 3E8000h-3EFFFFh 3F0000h-3F7FFFh 3F8000h-3FFFFFh 400000h-407FFFh 408000h-40FFFFh 410000h-417FFFh 418000h-41FFFFh 420000h-427FFFh 428000h-42FFFFh 430000h-437FFFh 438000h-43FFFFh 440000h-447FFFh 448000h-44FFFFh 450000h-457FFFh 458000h-45FFFFh 460000h-467FFFh 468000h-46FFFFh 470000h-477FFFh 478000h-47FFFFh 480000h-487FFFh 488000h-48FFFFh 490000h-497FFFh 498000h-49FFFFh 4A0000h-4A7FFFh 4A8000h-4AFFFFh 4B0000h-4B7FFFh A48000h-4BFFFFh Address Range (x32) 1C4000h-1C7FFFh 1C8000h-1CBFFFh 1CC000h-1CFFFFh 1D0000h-1D3FFFh 1D4000h-1D7FFFh 1D8000h-1DBFFFh 1DC000h-1DFFFFh 1E0000h-1E3FFFh 1E4000h-1E7FFFh 1E8000h-1EBFFFh 1EC000h-1EFFFFh 1F0000h-1F3FFFh 1F4000h-1F7FFFh 1F8000h-1FBFFFh 1FC000h-1FFFFFh 200000h-203FFFh 204000h-207FFFh 208000h-20BFFFh 20C000h-20FFFFh 210000h-213FFFh 214000h-217FFFh 218000h-21BFFFh 21C000h-21FFFFh 220000h-223FFFh 224000h-227FFFh 228000h-22BFFFh 22C000h-22FFFFh 230000h-233FFFh 234000h-237FFFh 238000h-23BFFFh 23C000h-23FFFFh 240000h-243FFFh 244000h-247FFFh 248000h-24BFFFh 24C000h-24FFFFh 250000h-253FFFh 254000h-257FFFh 258000h-25BFFFh 25C000h-25FFFFh
Bank
Sector SA120 SA121 SA122 SA123 SA124
Bank 2 (continued)
SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 SA142 SA143 SA144 SA145
Bank 3
SA146 SA147 SA148 SA149 SA150 SA151 SA152 SA153 SA154 SA155 SA156 SA157 SA158
16
AM29PDL128G
July 29, 2002
PRELIMINARY Table 5.
Sector Address (A21-A11) 10011000XXX 10011001XXX 10011010XXX 10011011XXX 10011100XXX 10011101XXX 10011110XXX 10011111XXX 10100000XXX 10100001XXX 10100010XXX 10100011XXX 10100100XXX 10100101XXX 10100110XXX 10100111XXX 10101000XXX 10101001XXX 10101010XXX 10101011XXX 10101100XXX 10101101XXX 10101110XXX 10101111XXX 10110000XXX 10110001XXX 10110010XXX 10110011XXX 10110100XXX 10110101XXX 10110110XXX 10110111XXX 10111000XXX 10111001XXX 10111010XXX 10111011XXX 10111100XXX 10111101XXX 10111110XXX
Sector Address Table (Continued)
Sector Size (Kwords/ Kdoublewords) 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 Address Range (x16) 4C0000h-4C7FFFh 4C8000h-4CFFFFh 4D0000h-4D7FFFh 4D8000h-4DFFFFh 4E0000h-4E7FFFh 4E8000h-4EFFFFh 4F0000h-4F7FFFh 4F8000h-4FFFFFh 500000h-507FFFh 508000h-50FFFFh 510000h-517FFFh 518000h-51FFFFh 520000h-527FFFh 528000h-52FFFFh 530000h-537FFFh 538000h-53FFFFh 540000h-547FFFh 548000h-54FFFFh 550000h-557FFFh 558000h-55FFFFh 560000h-567FFFh 568000h-56FFFFh 570000h-577FFFh 578000h-57FFFFh 580000h-587FFFh 588000h-58FFFFh 590000h-597FFFh 598000h-59FFFFh 5A0000h-5A7FFFh 5A8000h-5AFFFFh 5B0000h-5B7FFFh 5B8000h-5BFFFFh 5C0000h-5C7FFFh 5C8000h-5CFFFFh 5D0000h-5D7FFFh 5D8000h-5DFFFFh 5E0000h-5E7FFFh 5E8000h-5EFFFFh 5F0000h-5F7FFFh Address Range (x32) 260000h-263FFFh 264000h-267FFFh 268000h-26BFFFh 26C000h-26FFFFh 270000h-273FFFh 274000h-277FFFh 278000h-27BFFFh 27C000h-27FFFFh 280000h-283FFFh 284000h-287FFFh 288000h-28BFFFh 28C000h-28FFFFh 290000h-293FFFh 294000h-297FFFh 298000h-29BFFFh 29C000h-29FFFFh 2A0000h-2A3FFFh 2A4000h-2A7FFFh 2A8000h-2ABFFFh 2AC000h-2AFFFFh 2B0000h-2B3FFFh 2B4000h-2B7FFFh 2B8000h-2BBFFFh 2BC000h-2BFFFFh 2C0000h-2C3FFFh 2C4000h-2C7FFFh 2C8000h-2CBFFFh 2CC000h-2CFFFFh 2D0000h-2D3FFFh 2D4000h-2D7FFFh 2D8000h-2DBFFFh 2DC000h-2DFFFFh 2E0000h-2E3FFFh 2E4000h-2E7FFFh 2E8000h-2EBFFFh 2EC000h-2EFFFFh 2F0000h-2F3FFFh 2F4000h-2F7FFFh 2F8000h-2FBFFFh
Bank
Sector SA159 SA160 SA161 SA162 SA163 SA164 SA165 SA166 SA167 SA168 SA169 SA170 SA171 SA172 SA173 SA174 SA175
Bank 3 (continued)
SA176 SA177 SA178 SA179 SA180 SA181 SA182 SA183 SA184 SA185 SA186 SA187 SA188 SA189 SA190 SA191 SA192 SA193 SA194 SA195 SA196 SA197
July 29, 2002
AM29PDL128G
17
PRELIMINARY Table 5.
Sector Address (A21-A11) 10111111XXX 11000000XXX 11000001XXX 11000010XXX 11000011XXX 11000100XXX 11000101XXX 11000110XXX 11000111XXX 11001000XXX 11001001XXX 11001010XXX 11001011XXX 11001100XXX 11001101XXX 11001110XXX 11001111XXX 11010000XXX 11010001XXX 11010010XXX 11010011XXX 11010100XXX 11010101XXX 11010110XXX 11010111XXX 11011000XXX 11011001XXX 11011010XXX 11011011XXX 11011100XXX 11011101XXX 11011110XXX 11011111XXX
Sector Address Table (Continued)
Sector Size (Kwords/ Kdoublewords) 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 Address Range (x16) 5F8000h-5FFFFFh 600000h-607FFFh 608000h-60FFFFh 610000h-617FFFh 618000h-61FFFFh 620000h-627FFFh 628000h-62FFFFh 630000h-637FFFh 638000h-63FFFFh 640000h-647FFFh 648000h-64FFFFh 650000h-657FFFh 658000h-65FFFFh 660000h-667FFFh 668000h-66FFFFh 670000h-677FFFh 678000h-67FFFFh 680000h-687FFFh 688000h-68FFFFh 690000h-697FFFh 698000h-69FFFFh 6A0000h-6A7FFFh 6A8000h-6AFFFFh 6B0000h-6B7FFFh 6B8000h-6BFFFFh 6C0000h-6C7FFFh 6C8000h-6CFFFFh 6D0000h-6D7FFFh 6D8000h-6DFFFFh 6E0000h-6E7FFFh 6E8000h-6EFFFFh 6F0000h-6F7FFFh 6F8000h-6FFFFFh Address Range (x32) 2FC000h-2FFFFFh 300000h-303FFFh 304000h-307FFFh 308000h-30BFFFh 30C000h-30FFFFh 310000h-313FFFh 314000h-317FFFh 318000h-31BFFFh 31C000h-31FFFFh 320000h-323FFFh 324000h-327FFFh 328000h-32BFFFh 32C000h-32FFFFh 330000h-333FFFh 334000h-337FFFh 338000h-33BFFFh 33C000h-33FFFFh 340000h-343FFFh 344000h-347FFFh 348000h-34BFFFh 34C000h-34FFFFh 350000h-353FFFh 354000h-357FFFh 358000h-35BFFFh 35C000h-35FFFFh 360000h-363FFFh 364000h-367FFFh 368000h-36BFFFh 36C000h-36FFFFh 370000h-373FFFh 374000h-377FFFh 378000h-37BFFFh 37C000h-37FFFFh
Bank
Sector SA198 SA199 SA200 SA201 SA202 SA203 SA204 SA205 SA206 SA207 SA208 SA209 SA210 SA211
Bank 3 (continued)
SA212 SA213 SA214 SA215 SA216 SA217 SA218 SA219 SA220 SA221 SA222 SA223 SA224 SA225 SA226 SA227 SA228 SA229 SA230
18
AM29PDL128G
July 29, 2002
PRELIMINARY Table 5.
Sector Address (A21-A11) 11100000XXX 11100001XXX 11100010XXX 11100011XXX 11100100XXX 11100101XXX 11100110XXX 11100111XXX 11101000XXX 11101001XXX 11101010XXX 11101011XXX 11101100XXX 11101101XXX 11101110XXX 11101111XXX 11110000XXX 11110001XXX 11110010XXX 11110011XXX 11110100XXX 11110101XXX 11110110XXX 11110111XXX 11111000XXX 11111001XXX 11111010XXX 11111011XXX 11111100XXX 11111101XXX 11111110XXX 11111111000 11111111001 11111111010 11111111011 11111111100 11111111101 11111111110 11111111111
Sector Address Table (Continued)
Sector Size (Kwords/ Kdoublewords) 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 32/16 4/2 4/2 4/2 4/2 4/2 4/2 4/2 4/2 Address Range (x16) 700000h-707FFFh 708000h-70FFFFh 710000h-717FFFh 718000h-71FFFFh 720000h-727FFFh 728000h-72FFFFh 730000h-737FFFh 738000h-73FFFFh 740000h-747FFFh 748000h-74FFFFh 750000h-757FFFh 758000h-75FFFFh 760000h-767FFFh 768000h-76FFFFh 770000h-777FFFh 778000h-77FFFFh 780000h-787FFFh 788000h-78FFFFh 790000h-797FFFh 798000h-79FFFFh 7A0000h-7A7FFFh 7A8000h-7AFFFFh 7B0000h-7B7FFFh 7B8000h-7BFFFFh 7C0000h-7C7FFFh 7C8000h-7CFFFFh 7D0000h-7D7FFFh 7D8000h-7DFFFFh 7E0000h-7E7FFFh 7E8000h-7EFFFFh 7F0000h-7F7FFFh 7F8000h-7F8FFFh 7F9000h-7F9FFFh 7FA000h-7FAFFFh 7FB000h-7FBFFFh 7FC000h-7FCFFFh 7FD000h-7FDFFFh 7FE000h-7FEFFFh 7FF000h-7FFFFFh Address Range (x32) 380000h-383FFFh 384000h-387FFFh 388000h-38BFFFh 38C000h-38FFFFh 390000h-393FFFh 394000h-397FFFh 398000h-39BFFFh 39C000h-39FFFFh 3A0000h-3A3FFFh 3A4000h-3A7FFFh 3A8000h-3ABFFFh 3AC000h-3AFFFFh 3B0000h-3B3FFFh 3B4000h-3B7FFFh 3B8000h-3BBFFFh 3BC000h-3BFFFFh 3C0000h-3C3FFFh 3C4000h-3C7FFFh 3C8000h-3CBFFFh 3CC000h-3CFFFFh 3D0000h-3D3FFFh 3D4000h-3D7FFFh 3D8000h-3DBFFFh 3DC000h-3DFFFFh 3E0000h-3E3FFFh 3E4000h-3E7FFFh 3E8000h-3EBFFFh 3EC000h-3EFFFFh 3F0000h-3F3FFFh 3F4000h-3F7FFFh 3F8000h-3FBFFFh 3FC000h-3FC7FFh 3FC800h-3FCFFFh 3FD000h-3FD7FFh 3FD800h-3FDFFFh 3FE000h-3FE7FFh 3FE800h-3FEFFFh 3FF000h-3FF7FFh 3FF800h-3FFFFFh
Bank
Sector SA231 SA232 SA233 SA234 SA235 SA236 SA237 SA238 SA239 SA240 SA241 SA242 SA243 SA244 SA245 SA246 SA247 SA248
Bank 4
SA249 SA250 SA251 SA252 SA253 SA254 SA255 SA256 SA257 SA258 SA259 SA260 SA261 SA262 SA263 SA264 SA265 SA266 SA267 SA268 SA269
Note: The address range is A21:A-1 in word mode (WORD#=VIL) or A21:A0 in double word mode (WORD#=VIH). Address bits A21:A11 uniquely select a sector; address bits A21:A19 uniquely select a bank.
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AM29PDL128G
19
PRELIMINARY Table 6.
Device AM29PDL128G
SecSi Sector Addresses
Sector Size 128 words/64 double words (x32) Address Range 000000h-00003Fh (x16) Address Range 000000h-00007Fh
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7-DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programm ing algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins must be as shown in Table 7. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table 5). Table 7 shows the remaining address bits that are don't care. When all necessary bits have been set as required, the programming equipment may then Table 7.
A21 to A11 X
read the corresponding identifier code on DQ7-DQ0. However, the autoselect codes can also be accessed in-system through the command register, for instances when the device is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in Tables 14 and 16. Note that if a Bank Address (BA) on address bits A21, A20, and A19 is asserted during the third write cycle of the autoselect command, the host system can read autoselect data that bank and then immediately read array data from the other bank, without exiting the autoselect mode. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Tables 14 and 16. This method does not require VID. Refer to the Autoselect Command Sequence section for more information.
Autoselect Codes (High Voltage Method)
A5 to A4 X DQ31 to DQ8 A3 L L L H H H H A2 L L H H L A1 L L H H H A0 L H L H L
(Word/Double Word)
Description Manufacturer ID: AMD Read Cycle 1 Read Cycle 2 Read Cycle 3 Sector Protection Verification SecSi Indicator Bit (DQ7)
CE# OE# WE# L L H
A10 X
A9 VID
A8 X
A7 X
A6 L L
DQ7 to DQ0 01h 7Eh 0Dh 00h 01h (protected), 00h (unprotected) 80h (factory locked), 00h (not factory locked)
000000h 22h/ 222222h 22h/ 222222h 22h/ 222222h 00h/ 000000h 00h/ 000000h
Device ID
L
L
H
X
X
VID
X
L
L L
L
L
H
SA
X
VID
X
L
L
L
L
H
X
X
VID
X
X
L
X
L
L
H
H
Legend: L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA = Sector Address, X = Don't care. Note: The autoselect codes may also be accessed in-system via command sequences.
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PRELIMINARY Table 8.
Sector Group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 A21 0 0 0 0 0 0 0 0 A20 0 0 0 0 0 0 0 0 A19 0 0 0 0 0 0 0 0
Sector Block Addresses for Protection/Unprotection
A18 0 0 0 0 0 0 0 0 A17 0 0 0 0 0 0 0 0 A16 0 0 0 0 0 0 0 0 A15 0 0 0 0 0 0 0 0 0 A14 0 0 0 0 0 0 0 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X SA11 to SA14 SA15 to SA18 SA19 to SA22 SA23 to SA26 SA27 to SA30 SA31 to SA34 SA35 to SA38 SA39 to SA42 SA43 to SA46 SA47 to SA50 SA51 to SA54 SA55 to SA58 SA59 to SA62 SA63 to SA66 SA67 to SA70 SA71 to SA74 SA75 to SA78 SA79 to SA82 SA83 to SA86 SA87 to SA90 SA91 to SA94 SA95 to SA98 SA99 to SA102 X X X SA8 to SA10 A13 0 0 0 0 1 1 1 1 A12 0 0 1 1 0 0 1 1 A11 0 1 0 1 0 1 0 1 Sectors SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7
SGA8
0
0
0
0
0
0
1 1
SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 SGA17 SGA18 SGA19 SGA20 SGA21 SGA22 SGA23 SGA24 SGA25 SGA26 SGA27 SGA28 SGA29 SGA30 SGA31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
X X X X X X X X X X X X X X X X X X X X X X X
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AM29PDL128G
21
PRELIMINARY Table 8.
Sector Group SGA32 SGA33 SGA34 SGA35 SGA36 SGA37 SGA38 SGA39 SGA40 SGA41 SGA42 SGA43 SGA44 SGA45 SGA46 SGA47 SGA48 SGA49 SGA50 SGA51 SGA52 SGA53 SGA54 SGA55 SGA56 SGA57 SGA58 SGA59 SGA60 SGA61 SGA62 SGA63 SGA64 SGA65 A21 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A20 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
Sector Block Addresses for Protection/Unprotection (Continued)
A19 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 A18 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 A17 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 A16 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A15 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A14 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A13 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A12 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A11 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Sectors SA103 to SA106 SA107 to SA110 SA111 to SA114 SA115 to SA118 SA119 to SA122 SA123 to SA126 SA127 to SA130 SA131 to SA134 SA135 to SA138 SA139 to SA142 SA143 to SA146 SA147 to SA150 SA151 to SA154 SA155 to SA158 SA159 to SA162 SA163 to SA166 SA167 to SA170 SA171 to SA174 SA175 to SA178 SA179 to SA182 SA183 to SA186 SA187 to SA190 SA191 to SA194 SA195 to SA198 SA199 to SA202 SA203 to SA206 SA207 to SA210 SA211 to SA214 SA215 to SA218 SA219 to SA222 SA223 to SA226 SA227 to SA230 SA231 to SA234 SA235 to SA238
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AM29PDL128G
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PRELIMINARY Table 8.
Sector Group SGA66 SGA67 SGA68 SGA69 SGA70 A21 1 1 1 1 1 A20 1 1 1 1 1
Sector Block Addresses for Protection/Unprotection (Continued)
A19 1 1 1 1 1 A18 0 0 1 1 1 A17 1 1 0 0 1 A16 0 1 0 1 0 A15 X X X X X 0 A14 X X X X X 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 SA262 SA263 SA264 SA265 SA266 SA267 SA268 SA269 X X X SA259 to SA261 A13 X X X X X A12 X X X X X A11 X X X X X Sectors SA239 to SA242 SA243 to SA246 SA247 to SA250 SA251 to SA254 SA255 to SA258
SGA71
1
1
1
1
1
1
0 1
SGA72 SGA73 SGA74 SGA75 SGA76 SGA77 SGA78 SGA79
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
SECTOR PROTECTION
The AM29PDL128G features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups: Persistent Sector Protection A command sector protection method that replaces the old 12 V controlled protection method. Password Sector Protection A highly sophisticated protection method that requires a password before changes to certain sectors or sector groups are permitted WP# Hardware Protection A write protect pin that can prevent program or erase operations in sectors 0, 1, 268, and 269. All parts default to operate in the Persistent Sector Protection mode. The customer must then choose if the Persistent or Password Protection method is most desirable. There are two one-time programmable non-volatile bits that define which sector protection method will be used. If the customer decides to continue using the Persistent Sector Protection method, they must set the Persistent Sector Protection Mode Locking Bit. This will permanently set the part to operate only using Persistent Sector Protection. If the customer decides to use the password method, they must set the Password Mode Locking Bit. This will permanently set the part to operate only using password sector protection. It is important to remember that setting either the Persistent Sector Protection Mode Locking Bit or the Password Mode Locking Bit permanently selects the protection mode. It is not possible to switch between the two methods once a locking bit has been set. It is important that one mode is explicitly selected when the device is first programmed, rather than relying on the default mode alone. This is so that it is not possible for a system program or virus to later set the Password Mode Locking Bit, which would cause an unexpected shift from the default Persistent Sector Protection Mode into the Password Protection Mode. The WP# Hardware Protection feature is always available, independent of the software managed protection method chosen. The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at the factory prior to shipping the device through AMD's ExpressFlashTM Service. Contact an AMD representative for details. 23
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AM29PDL128G
PRELIMINARY It is possible to determine whether a sector is protected or unprotected. See Autoselect Mode for details. When the device is first powered on the DYBs power up cleared (sectors not protected). The Protection State for each sector is determined by the logical OR of the PPB and the DYB related to that sector. For the sectors that have the PPBs cleared, the DYBs control whether or not the sector is protected or unprotected. By issuing the DYB Write command sequences, the DYBs will be set or cleared, thus placing each sector in the protected or unprotected state. These are the so-called Dynamic Locked or Unlocked states. They are called dynamic states because it is very easy to switch back and forth between the protected and unprotected conditions. This allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. The DYBs maybe set or cleared as often as needed. The PPBs allow for a more static, and difficult to change, level of protection. The PPBs retain their state across power cycles because they are Non-Volatile. Individual PPBs are set with a command but must all be cleared as a group through a complex sequence of program and erasing commands. The PPBs are also limited to 100 erase cycles. The PPB Lock bit adds an additional level of protection. Once all PPBs are programmed to the desired settings, the PPB Lock may be set to "1". Setting the PPB Lock disables all program and erase commands to the Non-Volatile PPBs. In effect, the PPB Lock Bit locks the PPBs into their current state. The only way to clear the PPB Lock is to go through a power cycle. System boot code can determine if any changes to the PPB are needed e.g. to allow new system code to be downloaded. If no changes are needed then the boot code can set the PPB Lock to disable any further changes to the PBBs during system operation. The WP# protects the top two and bottom two sectors when at VIL. These sectors generally hold system boot code. The WP# pin can prevent any changes to the boot code that could override the choices made while setting up sector protection during system initialization. It is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. The sectors in the dynamic state are all unprotected. If there is a need to protect some of them, a simple DYB Write command sequence is all that is necessary. The DYB write command for the dynamic sectors switch the DYBs to signify protected and unprotected, respectively. If there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock bit must be disabled by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the
Persistent Sector Protection
The Persistent Sector Protection method replaces the old 12 V controlled protection method while at the same time enhancing flexibility by providing three different sector protection states: s Persistently Locked--A sector is protected and cannot be changed. s Dynamically Locked--The sector is protected and can be changed by a simple command s Unlocked--The sector is unprotected and can be changed by a simple command In order to achieve these states, three types of "bits" are going to be used: Persistent Protection Bit (PPB) A single Persistent (non-volatile) Protection Bit is assigned to a maximum four sectors (see the sector address tables for specific sector protection groupings). All 8 Kbyte boot-block sectors have individual sector Persistent Protection Bits (PPBs) for greater flexibility. Each PPB is individually modifiable through the PPB Write Command. Note: If a PPB requires erasure, all of the sector PPBs must first be preprogrammed prior to PPB erasing. All PPBs erase in parallel, unlike programming where individual PPBs are programmable. It is the responsibility of the user to perform the preprogramming operation. Otherwise, an already erased sector PPBs has the potential of being over-erased. There is no h ar d w ar e m ec h an ism to pr e v en t s e c to r P P Bs over-erasure. Persistent Protection Bit Lock (PPB Lock) A global volatile bit. When set to "1", the PPBs cannot be changed. When cleared ("0"), the PPBs are changeable. There is only one PPB Lock bit per device. The PPB Lock is cleared after power-up or hardware reset. There is no command sequence to unlock the PPB Lock. Dynamic Protection Bit (DYB) A volatile protection bit is assigned for each sector. After power-up or hardware reset, the contents of all DYBs is "0". Each DYB is individually modifiable through the DYB Write Command. When the parts are first shipped, the PPBs are cleared, the DYBs are cleared, and PPB Lock is defaulted to power up in the cleared state - meaning the PPBs are changeable.
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PRELIMINARY PPB lock bit once again will lock the PPBs, and the device operates normally again. Note: to achieve the best protection, it's recommended to execute the PPB lock bit set command early in the boot code, and protect the boot code by holding WP# = VIL. Table 9.
DYB 0 0 0 1 1 0 1 1 PPB 0 0 1 0 1 1 0 1
locking bit. This guarantees that a hacker could not place the device in password protection mode.
Password Protection Mode
The Password Sector Protection Mode method allows an even higher level of security than the Persistent Sector Protection Mode. There are two main differences between the Persistent Sector Protection and the Password Sector Protection Mode: s When the device is first powered on, or comes out of a reset cycle, the PPB Lock bit set to the locked state, rather than cleared to the unlocked state. s The only means to clear the PPB Lock bit is by writing a unique 64-bit Password to the device. The Password Sector Protection method is otherwise identical to the Persistent Sector Protection method. A 64-bit password is the only additional tool utilized in this method. The password is stored in the first eight bytes of the SecSi Sector. Once the Password Mode Locking Bit is set, the password is permanently set with no means to read, program, or erase it. The password is used to clear the PPB Lock bit. The Password Unlock command must be written to the flash, along with a password. The flash device internally compares the given password with the pre-programmed password. If they match, the PPB Lock bit is cleared, and the PPBs can be altered. If they do not match, the flash device does nothing. There is a built-in 2 s delay for each "password check." This delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password. Because the password occupies the first eight bytes of the SecSi Sector, the password must be programmed before either the password protection mode is selected or the SecSi Sector protection bit is programmed (to use both the SecSi Sector and Password Protection at the same time). See Utilizing Password and SecSi Sector Concurrently for more information.
Sector Protection Schemes
PPB Lock 0 1 0 0 0 1 1 1 Protected--PPB not changeable, DYB is changeable Protected--PPB and DYB are changeable Sector State Unprotected--PPB and DYB are changeable Unprotected--PPB not changable, DYB is changable
Table 9 contains all possible combinations of the DYBDYB, PPB, and PPB lock relating to the status of the sector. In summary, if the PPB is set, and the PPB lock is set, the sector is protected and the protection can not be removed until the next power cycle clears the PPB lock. If the PPB is cleared, the sector can be dynamically locked or unlocked. The DYB then controls whether or not the sector is protected or unprotected. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. A program command to a protected sector enables status polling for approximately 1 s before the device returns to read mode without having modified the contents of the protected sector. An erase command to a protected sector enables status polling for approximately 50 s after which the device returns to read mode without having erased the protected sector. The programming of the DYB, PPB, and PPB lock for a given sector can be verified by writing a DYB/PPB/PPB lock verify command to the device.
Password and Password Mode Locking Bit
In order to select the Password sector protection scheme, the customer must first program the password. AMD recommends that the password be somehow correlated to the unique Electronic Serial Number (ESN) of the particular flash device. Each ESN is different for every flash device; therefore each password should be different for every flash device. While programming in the password region, the customer may perform Password Verify operations. Once the desired password is programmed in, the customer must then set the Password Mode Locking Bit. This operation achieves two objectives:
Persistent Sector Protection Mode Locking Bit
Like the password mode locking bit, a Persistent Sector Protection mode locking bit exists to guarantee that the device remain in software sector protection. Once set, the Persistent Sector Protection locking bit prevents programming of the password protection mode
July 29, 2002
AM29PDL128G
25
PRELIMINARY 1. It permanently sets the device to operate using the Password Protection Mode. It is not possible to reverse this function. 2. It also disables all further commands to the password region. All program, and read operations are ignored. Both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. The user must be sure that the Password Protection method is desired when setting the Password Mode Locking Bit. More importantly, the user must be sure that the password is correct when the Password Mode Locking Bit is set. Due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. If the password is lost after setting the Password Mode Locking Bit, there will be no way to clear the PPB Lock bit. The Password Mode Locking Bit, once set, prevents reading the 64-bit password on the DQ bus and further password programming. The Password Mode Locking Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persistent Sector Protection Locking Bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. If the system asserts VIL on the WP# pin, the device disables program and erase functions in sectors 0, 1, 268, and 269 independent of whether it was previously protected or unprotected using High Voltage Sector Protection. If the system asserts VIH on the WP# pin, the device reverts to whether sectors 0, 1, 268, and 269 were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether they were previously protected or unprotected using High Voltage Sector Protection. Persistent Protection Bit Lock The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of the Password Mode Locking Bit after power-up reset. If the Password Mode Lock Bit is also set after a hardware reset (RESET# asserted) or a power-up reset. The ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to issue the Password Unlock command. Successful execution of the Password Unlock command clears the PPB Lock Bit, allowing for sector PPBs modifications. Asserting RESET#, taking the device through a power-on reset, or issuing the PPB Lock Bit Set command sets the PPB Lock Bit to a "1" when the Password Mode Lock Bit is not set. If the Password Mode Locking Bit is not set, including Persistent Protection Mode, the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Lock Bit is set by issuing the PPB Lock Bit Set command. Once set the only means for clearing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password Unlock command is ignored in Persistent Protection Mode.
64-bit Password
The 64-bit Password is located in its own memory space and is accessible through the use of the Password Program and Verify commands (see "Password Verify Command"). The password function works in conjunction with the Password Mode Locking Bit, which when set, prevents the Password Verify command from reading the contents of the password on the pins of the device.
Write Protect (WP#)
The Write Protect feature provides a hardware method of protecting sectors 0, 1, 268, and 269 without using VID. This function is provided by the WP# pin and overrides the previously discussed Sector Protection/Unprotection method.
High Voltage Sector Protection
Sector protection and unprotection may also be implemented using programming equipment. The procedure requires high voltage (VID) to be placed on the RESET# pin. Refer to Figure 1 for details on this procedure. Note that for sector unprotect, all unprotected sectors must first be protected prior to the first sector write cycle.
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AM29PDL128G
July 29, 2002
PRELIMINARY
START PLSCNT = 1 RESET# = VID Wait 1 s Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address START PLSCNT = 1 RESET# = VID Wait 1 s
Temporary Sector Unprotect Mode
No
First Write Cycle = 60h? Yes Set up sector address Sector Protect: Write 60h to sector address with A6-A0 = 0111010 Wait 150 s Verify Sector Protect: Write 40h to sector address with A6-A0 = 0111010 Read from sector address with A6-A0 = 0111010 No
No First Write Cycle = 60h? Yes All sectors protected? Yes Set up first sector address Sector Unprotect: Write 60h to sector address with A6-A0 = 1111010
Temporary Sector Unprotect Mode
Increment PLSCNT
Reset PLSCNT = 1
Wait 15 ms Verify Sector Unprotect: Write 40h to sector address with A6-A0 = 1111010
No No PLSCNT = 25? Yes Data = 01h?
Increment PLSCNT
Yes
No Yes No
Read from sector address with A6-A0 = 1111010 Set up next sector address
Device failed
Protect another sector? No Remove VID from RESET#
PLSCNT = 1000? Yes
Data = 00h? Yes
Device failed Write reset command
Last sector verified? Yes
No
Sector Protect Algorithm
Sector Protect complete
Sector Unprotect Algorithm
Remove VID from RESET#
Write reset command Sector Unprotect complete
Figure 1. In-System Sector Protection/ Sector Unprotection Algorithms
Note:These algorithms are valid only in Persistent Sector Protection mode. They are not valid in Password Protection Mode.
July 29, 2002
AM29PDL128G
27
PRELIMINARY
Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure 2 shows the algorithm, and Figure 23 shows the timing diagrams, for this feature.
AMD offers the device with the SecSi Sector either fa ctor y loc k ed o r c us tom er l oc k able . Th e factory-locked version is always protected when shipped from the factory, and has the SecSi Sector Indicator Bit permanently set to a "1." The customer-lockable version is shipped with the SecSi Sector unprotected, allowing customers to utilize the that sector in any manner they choose. The customer-lockable version has the SecSi Sector Indicator Bit permanently set to a "0." Thus, the SecSi Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory locked. The system accesses the SecSi Sector through a command sequence (see Enter SecSi Sector/Exit SecSi Sector Command Sequence). After the system has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. Factory Locked: SecSi Sector Programmed and Protected At the Factory In a factory locked device, the SecSi Sector is protected when the device is shipped from the factory. The SecSi Sector cannot be modified in any way. The device is preprogrammed with both a random number and a secure ESN. The SecSi Sector is located at add r e s se s 0 0 0 0 0 0 h - 0 0 0 0 7 F h i n w o r d m o de ( o r 000000h-00003Fh in double word mode). The device is available preprogrammed with one of the following: s A random, secure ESN only s Customer code through the ExpressFlash service s Both a random, secure ESN and customer code through the ExpressFlash service. Customers may opt to have their code programmed by AMD through the AMD ExpressFlash service. AMD programs the customer's code, with or without the random ESN. The devices are then shipped from AMD's factory with the SecSi Sector permanently locked. Contact an AMD representative for details on using AMD's ExpressFlash service. Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory If the security feature is not required, the SecSi Sector can be treated as an additional Flash memory space. The SecSi Sector can be read any number of times, but can be programmed and locked only once. Note that the accelerated programming (ACC) and unlock bypass functions are not available when programming the SecSi Sector.
START
RESET# = VID (Note 1) Perform Erase or Program Operations
RESET# = VIH
Temporary Sector Unprotect Completed (Note 2)
Notes: 1. All protected sectors unprotected (If WP# = VIL, sectors 0, 1, 268, and 269 will remain protected). 2. All previously protected sectors are protected once again.
Figure 2.
Temporary Sector Unprotect Operation
SecSiTM (Secured Silicon) Sector Flash Memory Region
The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 128 words (64 double words) in length, and uses a SecSi Sector Indicator Bit (DQ7) to indicate whether or not the SecSi Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field.
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PRELIMINARY The SecSi Sector area can be protected using one of the following procedures: s Write the three-cycle Enter SecSi Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 1, except that RESET# may be at either VIH or VID. This allows in-system protection of the SecSi Sector Region without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector. s Write the three-cycle Enter SecSi Sector Secure Region command sequence, and then use the alternate method of sector protection described in the Sector Protection section. Once the SecSi Sector is locked and verified, the system must write the Exit SecSi Sector Region command sequence to return to reading and writing the remainder of the array. The SecSi Sector lock must be used with caution since, once locked, there is no procedure available for unlocking the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way. SecSi Sector Protection Bit The SecSi Sector Protection Bit prevents programming of the SecSi Sector memory area. Once set, the SecSi Sector memory area contents are non-modifiable. Utilizing Password and SecSi Sector Concurrently The password must be stored in the first eight bytes of the SecSi Sector. Once the device is permanently locked into the Password Protection Mode, the erase, program, and read operation no longer work on those eight bytes of password in the SecSi Sector. Once the SecSi Sector protection bit is programmed, no location in the SecSi Sector may be programmed. To use both Password Protection and the SecSi Sector concurrently, the user must always program the password into the first eight bytes of the SecSi Sector before either the Password Protection Mode is selected or the SecSi Sector protection bit is programmed. Method 1 1. Enter the SecSi Sector by issuing the SecSi Sector Entry command. 2. Program the 64-bit password by issuing the Password Program and Password Verify commands 3. Lock the password by issuing the Password Protection Mode Locking Bit Program command. 4. Program the SecSi Sector, excluding bytes 0-7. 5. Lock the SecSi Sector by issuing the SecSi Sector Protection Bit Program command. 6. Exit the SecSi Sector by issuing the SecSi Sector Exit or Reset command
Note: Step 4 may be performed prior to step 2.
Method 2 1. Enter the SecSi Sector by issuing the SecSi Sector Entry command. 2. Program the entire SecSi Sector, including the first eight bytes contain the 64-bit password. 3. Lock the password by issuing the Password Protection Mode Locking Bit Program command. 4. Lock the SecSi Sector by issuing the SecSi Sector Protection Bit Program command. 5. Exit the SecSi Sector by issuing the SecSi Sector Exit or Reset command
Note: Step 4 may be performed prior to step 3.
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes. In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than V LKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when V CC is greater than VLKO. Write Pulse "Glitch" Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = V IH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
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PRELIMINARY
COMMON FLASH MEMORY INTERFACE (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 10-13. To terminate reading CFI data, Table 10.
Addresses (Double Word Mode) 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Addresses (Word Mode) 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h
the system must write the reset command. The CFI Query mode is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 10-13. The system must write the reset command to return the device to reading array data. For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide Web at http://www.am d.com/products/nvd/overview/cfi.html. Alternatively, contact an AMD representative for copies of these documents.
CFI Query Identification String
Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h
Description Query Unique ASCII string "QRY"
Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists)
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PRELIMINARY Table 11.
Addresses (Double Word Mode) 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Addresses (Word Mode) 36h 38h 3Ah 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch
System Interface String
Data 0027h 0036h 0000h 0000h 0004h 0000h 000Ah 0000h 0005h 0000h 0004h 0000h
Description VCC Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VCC Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical timeout per single byte/word write 2N s Typical timeout for Min. size buffer write 2N s (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported)
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PRELIMINARY Table 12.
Addresses (Double Word Mode) 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch Addresses (Word Mode) 4Eh 50h 52h 54h 56h 58h 5Ah 5Ch 5Eh 60h 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h 72h 74h 76h 78h
Device Geometry Definition
Data 0018h 0005h 0000h 0000h 0000h 0003h 0007h 0000h 0020h 0000h 00FDh 0000h 0000h 0001h 0007h 0000h 0020h 0000h 0000h 0000h 0000h 0000h Device Size = 2 byte
N
Description
Flash Device Interface description (refer to CFI publication 100) Max. number of byte in multi-byte write = 2N (00h = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100)
Erase Block Region 2 Information (refer to the CFI specification or CFI publication 100)
Erase Block Region 3 Information (refer to the CFI specification or CFI publication 100)
Erase Block Region 4 Information (refer to the CFI specification or CFI publication 100)
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PRELIMINARY Table 13.
Addresses (Double Word Mode) 40h 41h 42h 43h 44h 45h Addresses (Word Mode) 80h 82h 84h 86h 88h 8Ah
Primary Vendor-Specific Extended Query
Data 0050h 0052h 0049h 0031h 0033h 0004h
Description Query-unique ASCII string "PRI" Major version number, ASCII (reflects modifications to the silicon) Minor version number, ASCII (reflects modifications to the CFI table) Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Silicon Revision Number (Bits 7-2)
46h 47h 48h
8Ch 8Eh 90h
0002h 0001h 0001h
Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 01 =29F040 mode, 02 = 29F016 mode, 03 = 29F400, 04 = 29LV800 mode Simultaneous Operation 00 = Not Supported, X = Number of Sectors excluding Bank 1 Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag
49h
92h
0007h
4Ah 4Bh 4Ch 4Dh
94h 96h 98h 9Ah
00E7h 0000h 0002h 00B5h
4Eh
9Ch
0005h
4Fh
9Eh
0001h
00h = Uniform device, 01h = Uniform, 8 x 8 Kbit Top and Bottom, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Both Top and Bottom Program Suspend 0 = Not supported, 1 = Supported Bank Organization 00 = Data at 4Ah is zero, X = Number of Banks Bank 1 Region Information X = Number of Sectors in Bank 1 Bank 2 Region Information X = Number of Sectors in Bank 2 Bank 3 Region Information X = Number of Sectors in Bank 3 Bank 4 Region Information X = Number of Sectors in Bank 4
50h
A0h
0000h
57h
AEh
0004h
58h
B0h
*0027h
59h
B2h
*0060h
5Ah
B4h
*0060h
5Bh
B6h
0027h
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PRELIMINARY
COMMAND DEFINITIONS
Writing specific address and data commands or sequences into the command register initiates device operations. Tables 14-17 define the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the AC Characteristics section for timing diagrams. which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset co m m an d re tur n s th at b a nk t o t he e ra se- suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend).
Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the eras e-sus pend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. The system can read array data using the standard read timing, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Read-Only Operations table provides the read parameters, and Figure 11 shows the timing diagram.
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the autoselect command. The bank then enters the autoselect mode. The system may read any number of autoselect codes without reinitiating the command sequence. Tables 14 and 16 show the address and data requirements. To determine sector protection information, the system must write to the appropriate bank address (BA) and sector address (SA). Table 5 shows the address range and bank number associated with each sector. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend).
Reset Command
Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don't cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the bank to which the system was writing to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to 34
Enter SecSi Sector/Exit SecSi Sector Command Sequence
The SecSi Sector region provides a secured data area containing a random, eight word/four double word electronic serial number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region
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PRELIMINARY until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector comm an d s e q u e n c e r e t ur n s t he d e v i c e to n o rm a l operation. The SecSi Sector is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. Tables 15 and 17 show the address and data requirements for both command sequences. See also "SecSiTM (Secured Silicon) Sector Flash Memory Region" for further information. data is still "0." Only erase operations can convert a "0" to a "1." Unlock Bypass Command Sequence The unlock bypass feature allows the system to program data to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Tables 14 and 16 show the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the bank address and the data 90h. The second cycle need only contain the data 00h. The bank then returns to the read mode. The device offers accelerated program operations through the ACC pin. When the system asserts VHH on the ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the ACC pin to accelerate the operation. Note that the ACC pin must not be at VHH any operation other than accelerated programming, or device damage may result. In addition, the ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 3 illustrates the algorithm for the program operation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 16 for timing diagrams.
Double Word/Word Program Command Sequence
The system may program the device by double word or word, depending on the state of the WORD# pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Tables 14 and 16 show the address and data requirements for the program command sequence. When the Embedded Program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Write Operation Status section for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from "0" back to a "1." Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the
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PRELIMINARY Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Figure 4 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Figure 18 section for timing diagrams.
START
Write Program Command Sequence
Embedded Program algorithm in progress
Data Poll from System
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Tables 14 and 16 show the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 80 s occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 80 s, otherwise erasure may begin. Any sector erase address and command following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than S e ct o r E ra se o r E ra s e S u s p en d d u r i n g th e time-out period resets that bank to the read mode. The system must rewrite the command sequence and any additional addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3: Sector Erase Timer.). The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can determine the status of the erase operation by reading
Verify Data?
No
Yes No
Increment Address
Last Address?
Yes Programming Completed
Note: See Tables 14 and 16 for program command sequence.
Figure 3.
Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Tables 14 and 16 show the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to the Write Operation Status section for information on these status bits.
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PRELIMINARY DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to the Write Operation Status section for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Figure 4 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Figure 18 section for timing diagrams. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. Refer to the Autoselect Mode and Autoselect Command Sequence sections for details. To resume the sector erase operation, the system must write the Erase Resume command (address bits are don't care). The bank address of the erase-suspended bank is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing.
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the 80 s time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. Addresses are "don't-cares" when writing the Erase suspend command. After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Write Operation Status section for information on these status bits. After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard Double Word/Word Program operation. Refer to the Write Operation Status section for more information.
START
Write Erase Command Sequence (Notes 1, 2)
Data Poll to Erasing Bank from System
Embedded Erase algorithm in progress
No
Data = FFh?
Yes Erasure Completed
Notes: 1. See Tables 14 and 16 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer.
Figure 4.
Erase Operation
Password Program Command
The Password Program Command permits programming the password that is used as part of the hardware protection scheme. The actual password is 64-bits long. Depending upon the state of the WORD# pin, multiple Password Program Commands are required. For a x16 bit data bus, 4 Password Program commands are required to program the password. For
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PRELIMINARY a x32 bit data bus, 2 Password Program commands are required. The user must enter the unlock cycle, password program command (38h) and the program address/data for each portion of the password when programming. There is no special addressing order required for programming the password. Also, when the password is undergoing programming, Simultaneous Operation is disabled. Read operations to any memory location will return the programming status. Once prog ra m m in g is co m pl et e, t he use r m ust issu e a Read/Reset command to return the device to normal operation. Once the Password is written and verified, the Password Mode Locking Bit must be set in order to prevent verification. The Password Program Command is only capable of programming "0"s. Programming a "1" after a cell is programmed as a "0" results in a time-out by the Embedded Program AlgorithmTM with the cell remaining as a "0". The password is all F's when shipped from the factory. All 64-bit password combinations are valid as a password. Password Programming is permitted if the SecSi sector is enabled. The Password Protection Mode Locking Bit Program command is permitted if the SecSi sector is enabled.
Persistent Sector Protection Mode Locking Bit Program Command
The Persistent Sector Protection Mode Locking Bit Program Command programs the Persistent Sector Protection Mode Locking Bit, which prevents the Password Mode Locking Bit from ever being programmed. If the Persistent Sector Protection Mode Locking Bit is verified as programmed without margin, the Persistent Sector Protection Mode Locking Bit Program Command should be reissued to improve program margin. By disabling the program circuitry of the Password Mode Locking Bit, the device is forced to remain in the Persistent Sector Protection mode of operation, once this bit is set. Exiting the Persistent Protection Mode Locking Bit Program command is accomplished by writing the Read/Reset command. The Persistent Sector Protection Mode Locking Bit Program command is permitted if the SecSi sector is enabled.
Password Verify Command
The Password Verify Command is used to verify the Password. The Password is verifiable only when the Password Mode Locking Bit is not programmed. If the Password Mode Locking Bit is programmed and the user attempts to verify the Password, the device will always drive all F's onto the DQ data bus. The Password Verify command is permitted if the SecSi sector is enabled. Also, the device will not operate in Simultaneous Operation when the Password Verify command is executed. Only the password is returned regardless of the bank address. The lower two address bits (A0:A-1) are valid during the Password Verify. Writing the Read/Reset command returns the device back to normal operation.
SecSi Sector Protection Bit Program Command
The SecSi Sector Protection Bit Program Command programs the SecSi Sector Protection Bit, which prevents the SecSi sector memory from being cleared. If the SecSi Sector Protection Bit is verified as programmed without margin, the SecSi Sector Protection Bit Program Command should be reissued to improve program margin. Exiting the VCC-level SecSi Sector Protection Bit Program Command is accomplished by writing the Read/Reset command. The SecSi Sector Protection Bit Program command is permitted if the SecSi sector is enabled.
PPB Lock Bit Set Command
The PPB Lock Bit Set command is used to set the PPB Lock bit if it is cleared either at reset or if the Password Unlock command was successfully executed. There is no PPB Lock Bit Clear command. Once the PPB Lock Bit is set, it cannot be cleared unless the device is taken through a power-on clear or the Password Unlock command is executed. Upon setting the PPB Lock Bit, the PPBs are latched into the DYBs. If the Password Mode Locking Bit is set, the PPB Lock Bit status is reflected as set, even after a power-on reset cycle. In the Persistent Sector Protection mode, exiting the PPB Lock Bit Set command is accomplished by writing the Read/Reset command. The PPB Lock Bit Set command is permitted if the SecSi sector is enabled.
Password Protection Mode Locking Bit Program Command
The Password Protection Mode Locking Bit Program Command programs the Password Protection Mode Locking Bit, which prevents further verifies or updates to the Password. Once programmed, the Password Protection Mode Locking Bit cannot be erased! If the Password Protection Mode Locking Bit is verified as program without margin, the Password Protection Mode Locking Bit Program command can be executed to improve the program margin. Once the Password Protection Mode Locking Bit is programmed, the Persistent Sector Protection Locking Bit program circuitry is disabled, thereby forcing the device to remain in the Password Protection mode. Exiting the Mode Locking Bit Program command is accomplished by writing the Read/Reset command.
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PRELIMINARY
DYB Write Command
The DYB Write command is used to set or clear a DYB for a given sector. The high order address bits (A21-A11) are issued at the same time as the code 01h or 00h on DQ7-DQ0. All other DQ data bus pins are ignored during the data write cycle. The DYBs are modifiable at any time, regardless of the state of the PPB or PPB Lock Bit. The DYBs are cleared at power-up or hardware reset.Exiting the DYB Write command is accomplished by writing the Read/Reset command. The DYB Write command is permitted if the SecSi sector is enabled.
PPB Program Command
The PPB Program command is used to program, or set, a given PPB. Each PPB is individually programmed (but is bulk erased with the other PPBs). The specific sector address (A21-A11) are written at the same time as the program command 60h with A6 = 0. If the PPB Lock Bit is set and the corresponding PPB is set for the sector, the PPB Program command will not execute and the command will time-out without programming the PPB. After programming a PPB, two additional cycles are needed to determine whether the PPB has been programmed with margin. If the PPB has been programmed without margin, the program command should be reissued to improve the program margin. The PPB Program command is permitted if the SecSi sector is enabled. The PPB Program command does not follow the Embedded Program algorithm.
Password Unlock Command
The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs can be unlocked for modification, thereby allowing the PPBs to become accessible for modification. The exact password must be entered in order for the unlocking function to occur. This command cannot be issued any faster than 2 s at a time to prevent a hacker from running through the all 64-bit combinations in an attempt to correctly match a password. If the command is issued before the 2 s execution window for each portion of the unlock, the command will be ignored. The Password Unlock function is accomplished by writing Password Unlock command and data to the device to perform the clearing of the PPB Lock Bit. The password is 64 bits long, so the user must write the Password Unlock command 2 times for a x32 bit data bus and 4 times for a x16 data bus. Once the Password Unlock command is entered, the RY/BY# pin goes LOW indicating that the device is busy. Approximately 2 s is required for each portion of the unlock. Once the first portion of the password unlock completes (RY/BY# is not driven and DQ6 does not toggle when read), the Password Unlock command is issued again, only this time with the next part of the password. If WORD# = 1, the second Password Unlock command is the final command before the PPB Lock Bit is cleared (assuming a valid password). If WORD# = 0, this is the fourth Password Unlock command. In x16 mode, four Password Unlock commands are required to successfully clear the PPB Lock Bit. As with the first Password Unlock command, the RY/BY# signal goes LOW and reading the device results in the DQ6 pin toggling on successive read operations until complete. It is the responsibility of the microprocessor to keep track of the number of Password Unlock commands (2 for x32 bus and 4 for x16 bus), the order, and when to read the PPB Lock bit to confirm successful password unlock The Password Unlock command is permitted if the SecSi sector is enabled.
All PPB Erase Command
The All PPB Erase command is used to erase all PPBs in bulk. There is no means for individually erasing a specific PPB. Unlike the PPB program, no specific sector address is required. However, when the PPB erase command is written (60h) and A6 = 1, all Sector PPBs are erased in parallel. If the PPB Lock Bit is set the ALL PPB Erase command will not execute and the command will time-out without erasing the PPBs. After erasing the PPBs, two additional cycles are needed to determine whether the PPB has been erased with margin. If the PPBs has been erased without margin, the erase command should be reissued to improve the program margin. It is the responsibility of the user to preprogram all PPBs prior to issuing the All PPB Erase command. If the user attempts to erase a cleared PPB, over-erasure may occur making it difficult to program the PPB at a later time. Also note that the total number of PPB program/erase cycles is limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed. The All PPB Erase command is permitted if the SecSi sector is enabled.
DYB Write Command
The DYB Write command is used for setting the DYB, which is a volatile bit that is cleared at hardware reset. There is one DYB per sector. If the PPB is set, the sector is protected regardless of the value of the DYB. If the PPB is cleared, setting the DYB to a 1 protects the sector from programs or erases. Since this is a volatile bit, removing power or resetting the device will clear the DYBs. The bank address is latched when the command is written.
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PRELIMINARY The DYB Write command is permitted if the SecSi sector is enabled.
Sector Protection Status Command
The programming of either the PPB or DYB for a given sector or sector group can be verified by writing a Sector Protection Status command to the device. Note that there is no single command to independently verify the programming of a DYB or PPB for a given sector group.
PPB Lock Bit Set Command
The PPB Lock Bit set command is used for setting the PPB lock bit. During Password Protection mode, only the Password Unlock command can reset the PPB Lock Bit to 0. Otherwise, a power-up or hardware reset resets the PPB Lock Bit to 0.
PPB Lock Bit Status Command
The programming of the PPB Lock Bit can be verified by writing a PPB Lock Bit status verify command to the device.
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Command Definitions Tables
Table 14.
Command (Notes) Read (5) Reset (6) Manufacturer ID Autoselect (Note 7) Device ID (10) SecSi Sector Factory Protect Sector Group Protect Verify (9) Program Chip Erase Sector Erase Program/Erase Suspend (11) Program/Erase Resume (12) CFI Query (13) Accelerated Program (15) Configuration Register Verify Configuration Register Write (16) Unlock Bypass Entry (17) Unlock Bypass Program (17) Unlock Bypass Erase (17) Unlock Bypass CFI (13, 17) Unlock Bypass Reset (17) Cycles
Memory Array Command Definitions (x32 Mode)
Bus Cycles (Notes 1-4) Addr Data Addr Data Addr Data RA XXX 555 555 555 555 555 555 555 BA BA 55 XX 555 555 555 XX XX XX XX RD F0 AA AA AA AA AA AA AA B0 30 98 A0 AA AA AA A0 80 98 90 XX 00 PA 2AA 2AA 2AA PA XX PD 55 55 55 PD 10 (BA)5 55 555 555 C6 D0 20 (BA)XX XX RD WD 2AA 2AA 2AA 2AA 2AA 2AA 2AA 55 55 55 55 55 55 55 555 555 555 555 555 555 555 90 90 90 90 90 80 80 (BA)X00 (BA)X01 X03 SA02 PA 555 555 01 7E (see Note 8) XX00/ XX01 PD AA AA 2AA 2AA 55 55 555 SA 10 30 (BA)X0E 0D (BA)X0F 00 Addr Data Addr Data Addr Data
1 1 4 6 4 4 4 6 6 1 1 1 2 4 4 3 2 2 1 2
Legend: BA = Address of bank switching to autoselect mode, bypass mode, or erase operation. Determined by A21:A19, see Tables 4 and 5 for more detail. PA = Program Address (A21:A0). Addresses latch on falling edge of WE# or CE# pulse, whichever happens later. PD = Program Data (DQ15:DQ0) written to location PA. Data latches on rising edge of WE# or CE# pulse, whichever happens first. Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. 4. Shaded cells in table denote read cycles. All other cycles are write operations. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don't cares. No unlock or command cycles required when bank is reading array data. Reset command is required to return to reading array (or to erase-suspend-read mode if previously in Erase Suspend) when bank is in autoselect mode, or if DQ5 goes high (while bank is providing status information). Cycle 4 of autoselect command sequence is a read cycle. See Autoselect Command Sequence section for more information. The data is 80h for factory locked and 00h for not factory locked.
RA = Read Address (A21:A0). RD = Read Data (DQ15:DQ0) from location RA. SA = Sector Address (A21:A12) for verifying (in autoselect mode) or erasing. WD = Write Data. See "Configuration Register" definition for specific write data. Data latched on rising edge of WE#. X = Don't care
9.
The data is 00h for an unprotected sector group and 01h for a protected sector group.
10. Device ID must be read across cycles 4, 5, and 6. 11. System may read and program in non-erasing sectors, or enter autoselect mode, when in Program/Erase Suspend mode. Program/Erase Suspend command is valid only during a sector erase operation, and requires bank address. 12. Program/Erase Resume command valid only during Erase Suspend mode, and requires bank address. 13. Command valid when device is ready to read array data or when device is in autoselect mode. 14. ACC must be at VID during entire operation of command. 15. Command is ignored during any Embedded Program, Embedded Erase, or Suspend operation. 16. Unlock Bypass Entry command is required prior to any Unlock Bypass operation. Unlock Bypass Reset command is required to return to reading array.
5. 6.
7. 8.
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PRELIMINARY Table 15.
Command (Notes) Reset SecSi Sector Entry SecSi Sector Exit SecSi Protection Bit Program (5, 6) Password Program (5, 7, 8) Password Verify (8, 9) Password Unlock (7, 10, 11) PPB Program (6, 12) All PPB Erase (13, 14) PPB Lock Bit Set PPB Lock Bit Status (15) DYB Write (7) DYB Erase (7) DYB or PPB Status PPMLB Program (6,12) PPMLB Status (5) SPMLB Program (6,12) SPMLB Status (5) Cycles
Sector Protection Command Definitions (x32 Mode)
Bus Cycles (Notes 1-4) Addr Data Addr Data XXX 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 F0 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 (BA)555 (BA)555 (BA)555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 88 90 60 38 C8 28 60 60 78 58 48 48 58 60 60 60 60 SA SA SA SA PL PL SL SL RD(1) X1 X0 RD(0) 68 RD(0) 68 RD(0) SL 48 XX RD(0) PL 48 XX RD(0) XX SSA XX[0-1] 00 68 PD[0-1] SSA 48 XX RD(0) Addr Data Addr Data Addr Data Addr Data
1 3 4 6 4 4 4 6 6 3 4 4 4 4 6 4 6 4
PWA[0-1] PWD[0-1] PWA[0-1] PWD[0-1] (SA)WP (SA)EP 68 60 (SA)WP (SA)EP 48 40 (SA)WP RD(0) (SA)WP RD(0)
Legend: DYB = Dynamic Protection Bit SSA = SecSi Sector Address (A6:A0) is (0011010). PD[1:0] = Program Data. Password written in 2 portions. PPB = Persistent Protection Bit PWA = Password Address. A0 selects portion of password. PWD = Password Data being verified. PL = Password Protection Mode Lock Address (A5:A0) is (001010) RD(0) = Read Data DQ0 for protection indicator bit.
RD(1) = Read Data DQ1 for PPB Lock bit status. SA = Sector Address where security command applies. Address bits A21:A11 uniquely select any sector. SL = Persistent Protection Mode Lock Address (A5:A0) is (010010) WP = PPB Address (A6:A0) is (0111010) (Note 17) EP = PPB Erase Address (A6:A0) is (1111010) X = Don't care PPMLB = Password Protection Mode Locking Bit SPMLB = Persistent Protection Mode Locking Bit 9. Command sequence returns FFh if PPMLB is set.
1.
See Table 1 for description of bus operations.
2. 3. 4.
All values are in hexadecimal. Shaded cells in table denote read cycles. All other cycles are write operations. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don't cares. Reset command returns device to reading array. Cycle 4 programs addressed locking bit. Cycles 5 and 6 validate bit has been fully programmed when DQ0 = 1. If DQ0 = 0 in cycle 6, entire command sequence must be issued and verified again. Data is latched on rising edge of WE#. Entire command sequence must be executed for each portion of password.
10. Password is written over four consecutive cycles at addresses 0-3. 11. A 2 s timeout is required between any two portions of password. 12. A 100 s timeout is required between cycles 4 and 5. 13. A 1.2 ms timeout is required between cycles 4 and 5. 14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, entire command sequence must be issued and verified again. Before issuing erase command, all PPBs should be programmed to prevent PPBs overerasure. 15. DQ1 = 1 if PPB locked, 0 if unlocked. 16. For all other parts that use the Persistant Protection Bit (axcluding PDL640G), the WP address is 000010.
5. 6.
7. 8.
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PRELIMINARY Table 16.
Command (Notes) Read (5) Reset (6) Manufacturer ID Device ID (10) Autoselect (Note 7) SecSi Sector Factory Protect Sector Group Protect Verify (9) Program Chip Erase Sector Erase Program/Erase Suspend (11) Program/Erase Resume (12) CFI Query (13) Accelerated Program (15) Configuration Register Verify Configuration Register Write (16) Unlock Bypass Entry (17) Unlock Bypass Program (17) Unlock Bypass Erase (17) Unlock Bypass CFI (13, 17) Unlock Bypass Reset (17) Cycles
Memory Array Command Definitions (x16 Mode)
Bus Cycles (Notes 1-4) Addr Data Addr Data RA XXX 555 555 555 555 555 AAA AAA BA BA 55 XX AAA AAA AAA XX XX XX XX RD F0 AA AA AA AA AA AA AA B0 30 98 A0 AA AA AA A0 80 98 90 XX 00 PA 555 555 555 PA XX PD 55 55 55 PD 10 (BA)AAA AAA AAA C6 D0 20 (BA)XX XX RD WD 2AA 2AA 2AA 2AA 2AA 555 555 55 55 55 55 55 55 55 555 555 555 555 555 AAA AAA 90 90 90 90 90 80 80 (BA)X00 (BA)X01 X03 SA02 PA AAA AAA 01 7E (see Note 8) XX00/ XX01 PD AA AA 555 555 55 55 AAA SA 10 30 (BA)X0E 0D (BA)X0F 00 Addr Data Addr Data Addr Data Addr Data
1 1 4 6 4 4 4 6 6 1 1 1 2 4 4 3 2 2 1 2
Legend: BA = Address of bank switching to autoselect mode, bypass mode, or erase. Determined by A21:A19, see Tables 4 and 5 for more detail. PA = Program Address (A21:A-1). Addresses latch on falling edge of WE# or CE# pulse, whichever happens later. PD = Program Data (DQ15:DQ0) written to location PA. Data latches on rising edge of WE# or CE# pulse, whichever happens first. RA = Read Address (A21:A-1). Notes: 1. See Table 1 for description of bus operations. 2. 3. 4. All values are in hexadecimal. Shaded cells in table denote read cycles. All other cycles are write operations. During unlock and command cycles, when lower address bits are 555 or AAAh as shown in table, address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don't cares. No unlock or command cycles required when bank is reading array data. Reset command is required to return to reading array (or to erase-suspend-read mode if previously in Erase Suspend) when a bank is in autoselect mode, or if DQ5 goes high (while bank is providing status information). Cycle 4 of autoselect command sequence is a read cycle. See Autoselect Command Sequence section for more information. The data is 80h for factory locked and 00h for not factory locked.
RD = Read Data (DQ15:DQ0) from location RA. SA = Sector Address (A21:A12) for verifying (in autoselect mode) or erasing. WD = Write Data. See "Configuration Register" definition for specific write data. Data latched on rising edge of WE#. X = Don't care
9.
The data is 00h for an unprotected sector group and 01h for a protected sector group.
10. Device ID must be read across cycles 4, 5, and 6. 11. System may read and program in non-erasing sectors, or enter autoselect mode, when in Program/Erase Suspend mode. Program/Erase Suspend command valid only during a sector erase operation, and requires bank address. 12. Program/Erase Resume command valid only during Erase Suspend mode, and requires bank address. 13. Command is valid when device is ready to read array data or when device is in autoselect mode. 14. ACC must be at VID during entire operation of this command. 15. Command ignored during any Embedded Program, Embedded Erase, or Suspend operation. 16. Unlock Bypass Entry command required prior to any Unlock Bypass operation. Unlock Bypass Reset command is required to return to reading array.
5. 6.
7. 8.
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PRELIMINARY Table 17.
Command (Notes) Reset SecSi Sector Entry SecSi Sector Exit SecSi Protection Bit Program (5, 6) Password Program (5, 7, 8) Password Verify (8, 9) Password Unlock (7, 10, 11) PPB Program (6, 12) All PPB Erase (13, 14) PPB Lock Bit Set PPB Lock Bit Status (15) DYB Write (7) DYB Erase (7) DYB or PPB Status PPMLB Program (5, 6, 12) PPMLB Status (5) SPMLB Program (5, 6, 12) SPMLB Status (5) Cycles
Sector Protection Command Definitions (x16 Mode)
Bus Cycles (Notes 1-4) Addr Data Addr Data XXX AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA F0 AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA AA 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 555 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 (BA)AAA (BA)AAA (BA)AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA 88 90 60 38 C8 28 60 60 78 58 48 48 58 60 60 60 60 SA SA SA SA PL PL SL SL RD(1) X1 X0 RD(0) 68 RD(0) 68 RD(0) SL 48 XX RD(0) PL 48 XX RD(0) XX SSA XX[0-3] 00 68 PD[0-3] SSA 48 XX RD(0) Addr Data Addr Data Addr Data Addr Data
1 3 4 6 4 4 4 6 6 3 4 4 4 4 6 4 6 4
PWA[0-3] PWD[0-3] PWA[0-3] PWD[0-3] (SA)WP (SA)EP 68 60 (SA)WP (SA)EP 48 40 (SA)WP RD(0) (SA)WP RD(0)
Legend: DYB = Dynamic Protection Bit SSA = SecSi Sector Address (A6:A0) is (0011010). PD[3:0] = Program Data. Password written as four 16-bit sections. PPB = Persistent Protection Bit PWA = Password Address. A0:A-1 selects portion of password. PWD = Password Data being verified. PL = Password Protection Mode Lock Address (A5:A0) is (001010) RD(0) = Read Data DQ0 for protection indicator bit.
RD(1) = Read Data DQ1 for PPB Lock bit status. SA = Sector Address where security command applies. Address bits A21:A11 uniquely select any sector. SL = Persistent Protection Mode Lock Address (A5:A0) is (010010) WP = PPB Address (A6:A0) is (0111010) (Note 16) EP = PPB Erase Address (A6:A0) is (1111010) X = Don't care PPMLB = Password Protection Mode Locking Bit SPMLB = Persistent Protection Mode Locking Bit 9. Command sequence returns FFh if PPMLB is set.
1.
See Table 1 for description of bus operations.
2. 3. 4.
All values are in hexadecimal. Shaded cells in table denote read cycles. All other cycles are write operations. During unlock and command cycles, when lower address bits are 555 or AAAh as shown in table, address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don't cares. Reset command returns device to reading array. Cycle 4 programs addressed locking bit. Cycles 5 and 6 validate the bit has been fully programmed when DQ0 = 1. If DQ0 = 0 in cycle 6, the program command must be issued and verified again. Data is latched on rising edge of WE#. Entire command sequence must be executed for each portion of password.
10. Password is written over four consecutive cycles, at addresses 0-3. 11. A 2 s timeout is required between any two portions of password. 12. A 100 s timeout is required between cycles 4 and 5. 13. A 1.2 ms timeout is required between cycles 4 and 5. 14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, erase command must be issued and verified again. Before issuing erase command, all PPBs should be programmed in order to prevent PPB overerasure. 15. DQ1 = 1 if PPB locked, 0 if unlocked. 16. For all other parts that use the Persistant Protection Bit (excluding PDL640G), the WP address is 000010.
5. 6.
7. 8.
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WRITE OPERATION STATUS
The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 18 and the following subsections describe the function of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an Embedded Program or Erase operation is in progress or has been completed. vice has completed the program or erase operation a n d D Q7 h a s va l i d d a ta , th e d a t a o u t p u ts o n D Q31- DQ0 m ay be s ti ll inv ali d. Valid da ta o n DQ31-DQ0 (or DQ15-DQ0 for word mode) will appear on successive read cycles. Table 18 shows the outputs for Data# Polling on DQ7. Figure 5 shows the Data# Polling algorithm. Figure 20 in the AC Characteristics section shows the Data# Polling timing diagram.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 s, then that bank returns to the read mode. During the Embedded Erase algorithm, Data# Polling produces a "0" on DQ7. When the Embedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a "1" on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 s, then the bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ31-DQ0 (or DQ15-DQ0 for word mode) on the following read cycles. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ31-DQ16 (DQ15-DQ0 for word mode) while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the deNo START
Read DQ7-DQ0 Addr = VA
DQ7 = Data?
Yes
No
DQ5 = 1?
Yes Read DQ7-DQ0 Addr = VA
DQ7 = Data?
Yes
No FAIL PASS
Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5.
Figure 5.
Data# Polling Algorithm
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PRELIMINARY
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or one of the banks is in the erase-suspend-read mode. Table 18 shows the outputs for RY/BY#.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 18 shows the outputs for Toggle Bit I on DQ6. Figure 6 shows the toggle bit algorithm. Figure 21 in the "AC Characteristics" section shows the toggle bit timing diagrams. Figure 22 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II.
START
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 s, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data.
Read Byte (DQ0-DQ7) Address =VA Read Byte (DQ0-DQ7) Address =VA
Toggle Bit = Toggle? Yes
No
No
DQ5 = 1?
Yes Read Byte Twice (DQ0-DQ7) Address = VA
Toggle Bit = Toggle?
No
Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete
Note: The system should recheck the toggle bit even if DQ5 = "1" because the toggle bit may stop toggling as DQ5 changes to "1." See the subsections on DQ6 and DQ2 for more information.
Figure 6.
Toggle Bit Algorithm
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DQ2: Toggle Bit II
The "Toggle Bit II" on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 18 to compare outputs for DQ2 and DQ6. Figure 6 shows the toggle bit algorithm in flowchart form, and the section "DQ2: Toggle Bit II" explains the algorithm. See also the DQ6: Toggle Bit I subsection. Figure 21 shows the toggle bit timing diagram. Figure 22 shows the differences between DQ2 and DQ6 in graphical form.
not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 6).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a "1," indicating that the program or erase cycle was not successfully completed. The device may output a "1" on DQ5 if the system tries to program a "1" to a location that was previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a "1." Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a "0" to a "1." If the time between additional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor DQ3. See also the Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is "1," the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is "0," the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 18 shows the status of DQ3 relative to the other status bits.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ31-DQ0 (or DQ15-DQ0 for word mode) at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ31-DQ0 (or DQ15-DQ0 for word mode) on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has
July 29, 2002
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47
PRELIMINARY Table 18.
Status Embedded Program Algorithm Embedded Erase Algorithm Erase Erase-Suspend- Suspended Sector Read Non-Erase Suspended Sector Erase-Suspend-Program
Write Operation Status
DQ7 (Note 2) DQ7# 0 1 Data DQ7# DQ6 Toggle Toggle No toggle Data Toggle DQ5 (Note 1) 0 0 0 Data 0 DQ3 N/A 1 N/A Data N/A DQ2 (Note 2) No toggle Toggle Toggle Data N/A RY/BY# 0 0 1 1 0
Standard Mode Erase Suspend Mode
Notes: 1. DQ5 switches to `1' when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank.
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PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Plastic Packages . . . . . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . -65C to +125C Voltage with Respect to Ground VCC (Note 1) . . . . . . . . . . . . . . . . .-0.5 V to +4.0 V A9, OE#, and RESET# (Note 2) . . . . . . . . . . . . . . . . . . . .-0.5 V to +12.5 V ACC (Note 2) . . . . . . . . . . . . . . .-0.5 V to +10.5 V All other pins (Note 1) . . . . . . -0.5 V to VCC +0.5 V Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may overshoot V SS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. See Figure 7. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 8. 2. Minimum DC input voltage on pins A9, OE#, RESET#, and ACC is -0.5 V. During voltage transitions, A9, OE#, ACC, and RESET# may overshoot V SS to -2.0 V for periods of up to 20 ns. See Figure 7. Maximum DC input voltage on pin A9, OE#, and RESET# is +12.5 V which may overshoot to +14.0 V for periods up to 20 ns. Maximum DC input voltage on ACC is +9.5 V which may overshoot to +12.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. +0.8 V -0.5 V -2.0 V 20 ns 20 ns 20 ns
Figure 7. Maximum Negative Overshoot Waveform
20 ns VCC +2.0 V VCC +0.5 V 2.0 V 20 ns 20 ns
Figure 8. Maximum Positive Overshoot Waveform
OPERATING RANGES
Industrial (I) Devices Ambient Temperature (TA) . . . . . . . . . -40C to +85C Extended (E) Devices Ambient Temperature (TA) . . . . . . . . -55C to +125C Supply Voltages VCC for full regulated range . . . . . . . . . . 3.0 V to 3.6 V VCC for full voltage range . . . . . . . . . . . . 2.7 V to 3.6 V VIO (see Note) . . . . . . . . . . . . . . . . . . . . 2.7 V to 3.6 V
Note: For all AC and DC specifications, VIO = VCC; contact AMD for other VIO options. Operating ranges define those limits between which the functionality of the device is guaranteed.
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PRELIMINARY
DC CHARACTERISTICS CMOS Compatible
Parameter Symbol ILI ILIT ILO Parameter Description Input Load Current A9, OE#, RESET# Input Load Current Output Leakage Current Test Conditions VIN = VSS to VCC, VCC = VCC max VCC = VCC max; VID= 12.5 V VOUT = VSS to VCC, OE# = VIH VCC = VCC max 1 MHz 5 MHz 10 MHz 1 MHz 5 MHz 4.5 20 38 9 37 17 1.5 1.5 1.5 Word CE# = VIL, OE# = VIH Dbl. Word Word CE# = VIL, OE# = VIH CE# = VIL, OE# = VIH -0.5 0.7 x VCC VCC = 3.0 V 10% VCC = 3.0 V 10% IOL = 4.0 mA, VCC = VCC min IOH = -2.0 mA, VCC = VCC min IOH = -100 A, VCC = VCC min 0.85 VIO VIO-0.4 2.3 2.5 V 8.5 11.5 Dbl. Word 30 30 21 21 17 Min Typ Max 1.0 35 1.0 9 40 45 18 mA 45 35 5 5 5 45 mA 45 45 mA 45 35 0.8 VCC + 0.3 9.5 12.5 0.45 mA V V V V V V mA A A A mA Unit A A A
ICC1
VCC Active Inter-page Read Current, Word/Double Word Modes CE# = VIL, OE# = VIH (Notes 1, 2) VCC Active Intra-page Read Current, CE# = VIL, OE# = VIH Word/Double Word Modes (Note 2)
ICC2 ICC3 ICC4 ICC5 ICC6
VCC Active Write Current (Notes 2, 3) CE# = VIL, OE# = VIH, WE# = VIL VCC Standby Current (Note 2) VCC Reset Current (Note 2) Automatic Sleep Mode (Notes 2, 4) VCC Active Read-While-Program Current (Notes 1, 2) VCC Active Read-While-Erase Current (Notes 1, 2) VCC Active Program-While-EraseSuspended Current (Notes 2, 5) Input Low Voltage Input High Voltage Voltage for ACC Program Acceleration Voltage for Autoselect and Temporary Sector Unprotect Output Low Voltage Output High Voltage Low VCC Lock-Out Voltage (Note 5) CE#, RESET# = VCC 0.3 V RESET# = VSS 0.3 V VIH = VCC 0.3 V; VIL = VSS 0.3 V
ICC7 ICC8 VIL VIH VHH VID VOL VOH1 VOH2 VLKO
Notes: 1. The ICC current listed is typically less than 4mA/MHz, with OE# at VIH. 2. Maximum ICC specifications are tested with VCC = VCCmax. 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 5. Not 100% tested.
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PRELIMINARY
TEST CONDITIONS
Table 19.
3.3 V Test Condition Output Load Output Load Capacitance, CL (including jig capacitance) CL 6.2 k Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels
Test Specifications
70R, 70, 80, 90 1 TTL gate 30 5 0.0-3.0 1.5 1.5 pF ns V V V Unit
Device Under Test
2.7 k
Note: Diodes are IN3064 or equivalent
Figure 9.
Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) OUTPUTS
KS000010-PAL
3.0 V 0.0 V
Input
1.5 V
Measurement Level
1.5 V
Output
Figure 10.
Input Waveforms and Measurement Levels
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PRELIMINARY
AC CHARACTERISTICS Read-Only Operations
Parameter JEDEC tAVAV tAVQV tELQV Std. tRC tACC tCE tPACC tGLQV tEHQZ tGHQZ tAXQX tOE tDF tDF tOH Description Read Cycle Time (Note 1) Address to Output Delay Chip Enable to Output Delay Page Access Time Output Enable to Output Delay Chip Enable to Output High Z (Notes 1, 3) Output Enable to Output High Z (Notes 1, 3) Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First Read tOEH Output Enable Hold Time (Note 1) Toggle and Data# Polling CE#, OE# = VIL OE# = VIL Test Setup Min Max Max Max Max Max Max Min Min Min Speed Options 70R, 70 70 70 70 25 25 25 25 5 0 10 80 80 80 80 30 30 30 30 5 90 90 90 90 35 35 30 30 5 Unit ns ns ns ns ns ns ns ns ns ns
Notes: 1. Not 100% tested. 2. See Figure 9 and Table 19 for test specifications 3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC/2. The time from OE# high to the data bus driven to VCC/2 is taken as tDF.
.
tRC Addresses CE# tRH tRH OE# tOEH WE# HIGH Z Outputs RESET# RY/BY# Output Valid tCE tOH HIGH Z tOE tDF Addresses Stable tACC
0V
Figure 11.
Read Operation Timings
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July 29, 2002
PRELIMINARY
AC CHARACTERISTICS
A21-A3
Same Page
A2-A-1
Aa
tACC
Ab
tPACC
Ac
tPACC tPACC
Ad
Data Bus CE# OE#
Figure 12.
Qa
Qb
Qc
Qd
Page Read Operation Timings
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53
PRELIMINARY
AC CHARACTERISTICS Hardware Reset (RESET#)
Parameter JEDEC Std tReady tReady tRP tRH tRPD tRB Description RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) RESET# Pulse Width Reset High Time Before Read (See Note) RESET# Low to Standby Mode RY/BY# Recovery Time Max Max Min Min Min Min All Speed Options 20 500 500 50 20 0 Unit s ns ns ns s ns
Note: Not 100% tested.
RY/BY#
CE#, OE# tRH RESET# tRP tReady
Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms
tReady RY/BY# tRB CE#, OE#
RESET# tRP
Figure 13.
Reset Timings
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PRELIMINARY
AC CHARACTERISTICS Word/Double Word Configuration (WORD#)
Parameter JEDEC Std tELFL/tELFH tFLQZ tFHQV Description CE# to WORD# Switching Low or High WORD# Switching Low to Output HIGH Z WORD# Switching High to Output Active Max Max Min 30 70 Speed Options 70R, 70 80 5 30 80 30 90 90 Unit ns ns ns
CE#
OE#
WORD# tELFL DQ15-DQ0
Data Output
Output
Switching from double word mode to word mode
DQ30-DQ16
Output
DQ31/A-1
Output
Address Input
tFLQZ tELFH WORD# Switching from word mode to double word mode
DQ30-DQ16 DQ15-DQ0
Output
Output
Output
DQ31/A-1
Address Input
Output
tFHQV
Figure 14.
WORD# Timings for Read Operations
CE# The falling edge of the last WE# signal WE#
WORD#
tSET (tAS)
tHOLD (tAH)
Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.
Figure 15.
WORD# Timings for Write Operations
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PRELIMINARY
AC CHARACTERISTICS Erase and Program Operations
Parameter JEDEC tAVAV tAVWL Std. tWC tAS tASO tWLAX tAH tAHT tDVWH tWHDX tDS tDH tOEPH tGHWL tELWL tWHEH tWLWH tWHDL tGHWL tCS tCH tWP tWPH tSR/W tWHWH1 tWHWH1 Description Write Cycle Time (Note 1) Address Setup Time Address Setup Time to OE# low during toggle bit polling Address Hold Time Address Hold Time From CE# or OE# high during toggle bit polling Data Setup Time Data Hold Time Output Enable High during toggle bit polling Read Recovery Time Before Write (OE# High to WE# Low) CE# Setup Time CE# Hold Time Write Pulse Width Write Pulse Width High Latency Between Read and Write Operations Word Programming Operation (Note 2) Double Word Accelerated Programming Operation, Double Word or Word (Note 2) Sector Erase Operation (Note 2) VCC Setup Time (Note 1) Write Recovery Time from RY/BY# Program/Erase Valid to RY/BY# Delay Typ Typ Typ Min Min Max 16 10.5 0.2 50 0 90 s sec s ns ns Min Min Min Min Min Min Min Min Min Min Min Min Min Min Typ 35 12 Speed Options 70R, 70 70 80 80 0 15 45 0 35 0 20 0 0 0 35 30 0 12.6 s 45 15 90 90 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tWHWH1 tWHWH2
tWHWH1 tWHWH2 tVCS tRB tBUSY
Notes: 1. Not 100% tested. 2. See the "Erase And Programming Performance" section for more information.
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PRELIMINARY
AC CHARACTERISTICS
Program Command Sequence (last two cycles) tWC Addresses 555h tAS PA tAH CE# OE# tWP WE# tCS tDS Data tDH PD tBUSY RY/BY# Status DOUT tRB tWPH tWHWH1 PA PA Read Status Data (last two cycles)
tCH
A0h
VCC tVCS
otes: . PA = program address, PD = program data, DOUT is the true data at the program address. . Illustration shows device in word mode.
Figure 16.
Program Operation Timings
VHH
WP#/ACC
VIL or VIH tVHH tVHH
VIL or VIH
Figure 17.
Accelerated Program Timing Diagram
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PRELIMINARY
AC CHARACTERISTICS
Erase Command Sequence (last two cycles) tWC Addresses 2AAh tAS SA
555h for chip erase
Read Status Data
VA tAH
VA
CE#
OE# tWP WE# tCS tDS
tCH
tWPH
tWHWH2
tDH Data 55h 30h
10 for Chip Erase Status DOUT
tBUSY RY/BY# tVCS VCC
tRB
otes: . SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operation Status". . These waveforms are for the word mode.
Figure 18.
Chip/Sector Erase Operation Timings
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PRELIMINARY
AC CHARACTERISTICS
tWC Addresses tAS CE#
Valid PA
tRC
Valid RA
tWC
Valid PA
tWC
Valid PA
tAH tACC tCE tOE OE# tOEH tWP WE# tWPH tDS tDH Data
Valid In
tAS tCPH
tAH
tCP
tGHWL
tDF tOH
Valid Out Valid In Valid In
tSR/W
WE# Controlled Write Cycle Read Cycle CE# Controlled Write Cycles
Figure 19.
Back-to-back Read/Write Cycle Timings
tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ7
High Z
VA
VA
tOE tDF
Complement
Complement
True
Valid Data
High Z
DQ6-DQ0 tBUSY RY/BY#
Status Data
Status Data
True
Valid Data
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 20.
Data# Polling Timings (During Embedded Algorithms)
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PRELIMINARY
AC CHARACTERISTICS
tAHT Addresses tAHT tASO CE# tOEH WE# tOEPH OE# tDH DQ6/DQ2 Valid Data
Valid Status
tAS
tCEPH
tOE
Valid Status Valid Status
Valid Data
(first read) RY/BY#
(second read)
(stops toggling)
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle
Figure 21.
Toggle Bit Timings (During Embedded Algorithms)
Enter Embedded Erasing WE#
Erase Suspend Erase
Enter Erase Suspend Program Erase Suspend Program
Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
DQ6
DQ2 Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6.
Figure 22.
DQ2 vs. DQ6
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PRELIMINARY
AC CHARACTERISTICS Temporary Sector Unprotect
Parameter JEDEC Std tVIDR tVHH tRSP tRRB Description VID Rise and Fall Time (See Note) VHH Rise and Fall Time (See Note) RESET# Setup Time for Temporary Sector Unprotect RESET# Hold Time from RY/BY# High for Temporary Sector Unprotect Min Min Min Min All Speed Options 500 250 4 4 Unit ns ns s s
Note: Not 100% tested.
VID RESET# VIL or VIH tVIDR Program or Erase Command Sequence CE# tVIDR
VID
VIL or VIH
WE# tRSP RY/BY# tRRB
Figure 23.
Temporary Sector Unprotect Timing Diagram
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PRELIMINARY
AC CHARACTERISTICS
VID VIH
ESET#
SA, A6, A1, A0
Valid* Sector Group Protect/Unprotect
Valid* Verify 40h
Valid*
Data 1 s CE#
60h
60h
Status
Sector Group Protect: 150 s Sector Group Unprotect: 15 ms
WE#
OE#
* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 24. Sector/Sector Block Protect and Unprotect Timing Diagram
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PRELIMINARY
AC CHARACTERISTICS Alternate CE# Controlled Erase and Program Operations
Parameter JEDEC tAVAV tAVWL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 Std. tWC tAS tAH tDS tDH tGHEL tWS tWH tCP tCPH tWHWH1 Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time WE# Hold Time CE# Pulse Width CE# Pulse Width High Programming Operation (Note 2) Accelerated Programming Operation, Double Word or Word (Note 2) Sector Erase Operation (Note 2) Word Double Word Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Typ 45 35 Speed Options 70R, 70 70 80 80 0 45 35 0 0 0 0 35 30 12.6 s 16.6 10.5 0.2 s sec 45 45 90 90 Unit ns ns ns ns ns ns ns ns ns ns
tWHWH1 tWHWH2
tWHWH1 tWHWH2
Notes: 1. Not 100% tested. 2. See the "Erase And Programming Performance" section for more information.
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PRELIMINARY
AC CHARACTERISTICS
555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase
Data# Polling PA
Addresses tWC tWH WE# tGHEL OE# tCP CE# tWS tCPH tDS tDH Data tRH
A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase
tAS tAH
tWHWH1 or 2
tBUSY
DQ7#
DOUT
RESET#
RY/BY#
Notes: 1. Figure indicates last two bus cycles of a program or erase operation. 2. PA = program address, SA = sector address, PD = program data. 3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device. 4. Waveforms are for the word mode.
Figure 25.
Alternate CE# Controlled Write (Erase/Program) Operation Timings
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PRELIMINARY
ERASE AND PROGRAMMING PERFORMANCE
Parameter Sector Erase Time Chip Erase Time Double Word Program Time Word Program Time Accelerated Double Word Program Time Accelerated Word Program Time Chip Program Time (Note 3) Double Word Mode Word Mode Typ (Note 1) 0.2 100 16.6 12.6 14.5 10.5 69.6 105.7 330 210 120 240 208 sec 317 Max (Note 2) 10 Unit sec sec s s s s Excludes system level overhead (Note 5) Comments Excludes 00h programming prior to erasure (Note 4)
Notes: 1. Typical program and erase times assume the following conditions: 25C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90C, VCC = 2.7 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Tables 14-17 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) Input voltage with respect to VSS on all I/O pins VCC Current Min -1.0 V -1.0 V -100 mA Max 13 V VCC + 1.0 V +100 mA
Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
FORTIFIED BGA PACKAGE CAPACITANCE
Parameter Symbol CIN COUT CIN2 Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz. Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ TBD TBD TBD Max TBD TBD TBD Unit pF pF pF
DATA RETENTION
Parameter Description Minimum Pattern Data Retention Time 125C 20 Years Test Conditions 150C Min 10 Unit Years
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PRELIMINARY
PHYSICAL DIMENSIONS LAB080--80-Ball Fortified Ball Grid Array 15 x 10 mm package
D1 0.20 C 2X D A eD
K
J
H
G
F
E
D
C
B
A 8 7 6 SE 7
eE 5 E1 E 4 3 2
50
1 A1 CORNER ID. (INK OR LASER) A1 CORNER
1.00 0.5
0.
1.00 0.5 A1 CORNER
B 0.20 C
6
NXb 0.25 M C A B 0.10 M C
SD
7
TOP VIEW
2X
BOTTOM VIEW
0.25 C
SEATING PLANE
C
0.15 C
SIDE VIEW
NOTES UNLESS OTHERWISE SPECIFIED: PACKAGE JEDEC LAB 080 NOTE 1. 2. 3. PROFILE HEIGHT STANDOFF BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT 0.70 BALL DIAMETER BALL PITCH - D DIRECTION BALL PITCH - E DIRECTION SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS A PACKAGE OUTLINE TYPE 8. 6 4. 5. e REPRESENTS THE SOLDER BALL GRID PITCH . SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER BALLS. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C . SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 . ALL DIMENSIONS ARE IN MILLIMETERS . BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED).
N/A 15.00 mm x 10.00 mm PACKAGE SYMBOL MIN. NOM. MAX. A A1 A2 D E D1 --0.40 0.60 ------15.00 BSC. 10.00 BSC. 9.00 BSC. 7.00 BSC. 10 8 80 0.50 0.60 1.00 BSC. 1.00 BSC. 0.50 BSC. 1.40 -----
E1
MD ME N b eD eE SD/SE
7
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PRELIMINARY
REVISION SUMMARY Revision A (October 29, 2001)
Initial release. Password Unlock Command section: Modified second paragraph. PPB Lock Bit Set Command section: Modified entire section. Substantial modifications were made to the command definitions tables and notes, including the following: deleted the PPB Status command sequence; added bank address requirements to SecSi Sector command; separated memory array and sector protection command sequences for easier reference. DC Characteristics In Note 1 of the CMOS Compatible table, changed typical ICC current from 2 to 4mA/MHz. Changed ICC1 typical and maximum read currents, added currents for 10 MHz operation. Added specifications for intra-page read current. Changed ICC6 typical current to 30 mA.
Revision A+1 (November 13, 2001)
Simultaneous Operation Block Diagram Added drawing. Table 13, Primary Vendor-Specific Extended Query Corrected data for 4Dh and 4Eh addresses (double-word mode). Physical Dimensions Added LAB080 package drawing.
Revision A+2 (February 8, 2002)
Global Added 90 ns speed option. At this speed, tDF is 30 ns and tOH is 5 ns. For all speeds, changed typical word programming time to 8.6 s, and typical double word programming time to 12.6 s. Simultaneous Operation Block Diagram Deleted BYTE# input.
Revision B+1 (June 7, 2002)
Global Changed data sheet status from Advance Information to Preliminary. AC Characteristics: Read-only Operations table
Revision B (April 26, 2002)
Global Added 70R (regulated voltage range) to speed options. Ordering Information Added "V" to package marking. Device Bus Operations Corrected sector size references in sector address table. Password Protection Mode section: Clarified that first 8 bytes of SecSi Sector should be reserved for the password. Added description of using password and SecSi Sector concurrently. SecSi Sector Flash Memory Region Added section on using password and SecSi Sector concurrently. Table 13, Primary Vendor-Specific Extended Query Corrected data for addresses 4D and 4Eh. Command Definitions Deleted PPB Status Command section. Password Program Command section: Modified first paragraph.
Changed t O E for 90 ns speed from 40 to 35 ns. Changed tOH for 70 ns speeds from 4 to 5 ns. AC Characteristics: Erase and Program Operations table, Alternate CE# Controlled Erase and Program Operations table Changed t A SO for 70 ns speed from 15 to 12 ns. Changed t DS for 80 ns speed from 45 to 35 ns. Changed tOEPH from 20 to 10 ns. Changed all typical values from tWHWH1. Erase and Programming Performance Added or modified typical and maximum values to all parameters in table except for typical sector erase time.
Revision B+2 (July 29, 2002)
Global Changed Simultanous Operation Flash to Simultanous Read/ Write Flash. Changed all references to DPB to DYB. BGA Package Capacitance Replaced TSOP Pin Capacitance with FBGA Capacitance data. Table 7. Autoselect Codes (High Voltage Method) Changed the A5 to A4 and A3 Sector Protection Verification fields from L to H.
July 29, 2002
AM29PDL128G
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PRELIMINARY Table 9. Sector Protection Schemes Added field: Unprotected-PPB not changeable, DYB is changable. Figure 1. In-System Sector Protection/Sector Unprotection Algorithms Added Note Table 14. Memory Array Command Definitions (x32 Mode) Table 16. Memory Array Command Definitions (x16 Mode) Added SecSi Sector Factory Protect and Sector Group Protect Verify fields to tables. Added Notes 8 and 9 Changed the Autoselect Sector Group Protect Verify command variable from SA(3A) to SA02. Table 15. Sector Protection Command Definitions (x32 mode) Table 17. Sector Protection Comamnd Definitions (x16 mode) Changed variables in Cycle field for Password Program (from 5 to 4), PPMLB Status (from 6 to 4), and SPMLB Status (from 6 to 4). Added Note 17 FBGA Ball Capacitance Changed table from BGA Capacitance to Fortified BGA Capacitance and modified values within table to TBD. DC Characteristics Deleted the IACC specification row. Special Package Handling Instructions Changed the instructions to include molded packages (TSOP, BGA, PLCC, PDIP, SSOP). CFI Modified wording of last paragraph to read `reading array data".
Trademarks Copyright (c) 2002 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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AM29PDL128G
July 29, 2002

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